XRS10L620 Datasheet, PDF (16/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

XRS10L620 Rev 1.00
( IO67 = channel6&7, pointed by PCI Base Address Reg4, Reserved )
( MEM5 = pointed by PCI Base Address Reg5 )
Register Table
Register addr IO addr mapping MEM addr mapping
[13 : 00]
IOG+ [13 : 00]
MEM5+ [13 : 00]
[7F : 14]
IOG+ [7F : 14]
MEM5+ [7F : 14]
[9F : 80]
IOG+ [9F : 80]
NA
[FF : A0]
IOG+ [FF : A0]
MEM5+ [FF : A0]
[17F : 100] IO01+ [7F : 00] MEM5+ [17F : 100]
[1FF : 180] IO01+ [FF : 80] MEM5+ [1FF : 180]
Description
AHCI generic host control
Reserved
IDE channel registers
I2C, GIO, PHY, Test registers
AHCI SATA Channel 0 registers
AHCI SATA Channel 1 registers
6.3.1 Global host registers : (IOG + 00h to 0FFh)
Reg_000H (IOG+00h) : Host Capability (CAP)
Bit(s) R/W default Symbol
Description
31
30
29
28
27
26
25
24
23:20
19
18
17
16
15
14
13
12:08
07:05
04:00
R
1
S64A ^{Support 64-bit Addressing}
R
1
SNCQ ^{Support Native Queue}
R
0
Reserved
R
0
SIS ^{Support Interlock Switch}
R
RA2
depends
1 = support Stagger Spin-up
SSS default =0, if RA2 pull up
default =1, if RA2 pull down
R
0
SALP ^{Support Aggressive Link Power Management}
R
1
SAL ^{Support Active LED}
R
1
SCLO ^{Support Command List Override}
R 0010
ISS ^{Interface Speed Support.}
R
0
SNZO ^{Support Non-zero DMA offsets}
R
1
SAM ^{Support AHCI mode only, no legacy mode}
R
1
SPM ^{Support Port Multiplier, FIS base switching}
R
0
Reserved
R
0
PMD ^{Only support single DRQ block data transfer for PIO}
R
1
SSC ^{Slumber state capable}
R
1
PSC ^{Partial state capable}
R 11111 NCS ^{Support 32 command slots per channel}
R
0
Reserved
R 00001
NP ^{Support maximum of 2 ports}
Reg_004H (IOG+04h) : Global HBA Control (GHC)
Bit(s) R/W default Symbol
Description
31
R
1
AE ^{Software can only access the chip using AHCI}
15
1/20/2009