XRS10L620 Datasheet, PDF (18/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

XRS10L620 Rev 1.00
(The region is only IO port accessed, not available by memory access using MEM5 decoding)
Reg_088H to Reg_08DH (IOG+88h to 8Dh) : (RO)
Reserved to 00h
Reg_08EH (IOG+8Eh) :
Standard Parallel IDE alternate status and control register
Reg_08FH (IOG+8Fh) : (RO)
Reserved to 00h
Reg_090H (IOG+90h) : IDE DMA start/stop
Bit(s) R/W default
Description
31 RW 0 Test only for CH0 and CH1.
FIFO threshold to initiate PCI write － request for IDE channel
000 : 7/8 FIFO full,
100 : 3/8 FIFO full
30:28 RW 000 001 : 6/8 FIFO full,
101 : 2/8 FIFO full
010 : 5/8 FIFO full,
110 : 1/8 FIFO full
011 : 4/8 FIFO full,
111 : 1/8 FIFO full
27
R
0 Reserved
FIFO threshold to initiate PCI read memory request for IDE channel
000 : 7/8 FIFO empty,
100 : 3/8 FIFO empty
26:24 RW 000 001 : 6/8 FIFO empty,
101 : 2/8 FIFO empty
010 : 5/8 FIFO empty,
110 : 1/8 FIFO empty
011 : 4/8 FIFO empty,
111 : 1/8 FIFO empty
23:20 R 0000 Reserved for internal test
19
R
0 IDE FIFO‘NOT empty’ flag, 0 means empty
Latched IDE IRQ flag and also shown at Reg_008H bit8,
18 RWC 0
fill 1 to clear the bit, or cleared when IDE IRQ is cleared.
17 RW 0 IDE IOR/W split enable, 1 = split enable
16
R
0 PCI/PCIX IDE DMA is active
15 RW 0 Set 1 to output low to reset IDE; 0 to normal state
14 RW 0 Set 1 to disable all IDE pins output
13
R
0 Reserved
12
R
0 Reserved for DLLEN# pin
11 RW 0 1= enable IDE IRQ as PCI INTA# signal. Default 0=disable
17
1/20/2009