XRS10L620 Datasheet, PDF (14/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

XRS10L620 Rev 1.00
CFGM+42h,43h(R) : Power Management capabilities(PMC), default 0602H
CFGM+44h,45h(RW) : Power Management Control/Status Register(PMCSR)
Default 0000H
Bit [15:02]: all 0h, read only
Bit1,bit0 : Power State, read/write
00b is D0 state
01b is D1 state
10b is D2 state
11b is D3 hot state
CFGM+46h(R) : PMCSR_BSE register, default 00H
CFGM+47h(R) : Data register, default 00H
6.2 PCI-X Capabilities List Item :
CFGM+48h(R) : PCI-X capabilities ID, = 07h.
CFGM+49h(R) : Next Capability, = 00h
CFGM+4Ah(RW) : 16 bits PCI-X command register
Bit(s) R/W default
Description
15,14 R
00 Reserved
PCI-X Capabilities List Item Version.
13,12 R
00 ‘00’ means Version 0, without ECC support and Capabilities List Item size is
8 bytes
11:7 R 00000 Reserved
Maximum Outstanding Split Transactions.
‘010’ means Maximum Outstanding at one time as a requester is 3.
6:4 RW 010
Values below‘010’ means 1 outstanding only.
Other values are same as ‘010’.
Maximum Memory Read Byte Count.
‘01’ means Maximum byte count is 1024 for burst memory commands
3,2 RW 01
‘00’ means Maximum byte count is 512 for burst memory commands
Other values are same as‘01’.
Enable Relaxed Ordering
1
R
0
‘0’: The device never set the Relaxed Ordering attribute bit
Uncorrectable Data Error Recovery Enable.
0 RW 0
6.2.1 CFGM+4Ch(R) : 32 bits PCI-X Status Register
Bit(s) R/W default
Description
31
R
0 0 = PCI-X 533 not capable
13
1/20/2009