XRS10L620 Datasheet, PDF (15/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

XRS10L620 Rev 1.00
30
R
0 0 = PCI-X 266 not capable (Not a PCI-X mode 2 device)
Received Split Completion Error Message.
29 RWC 0 0 = No Split Completion error message received.
1 = A Split Completion error message has been received.
Designed Maximum Cumulative Read Size
‘010’ is 4KB(32 ADQs) cumulative outstanding when Maximum Memory
28:26 R 010 Read Byte Count register is assigned to 1024 bytes.
‘001’is 2KB(16 ADQs) cumulative outstanding when Maximum Memory
Read Byte Count register is assigned to 512 bytes.
25:23 R
Designed Maximum Outstanding Split Transactions.
010
‘010’ means Maximum Outstanding at one time as a requester is 3.
22,21 R
Designed Maximum Memory Read Byte Count.
01
‘01’ means Maximum byte count is 1024 for burst memory commands
20
R
Device Complexity
0
0 = simple device 1 = bridge device
Unexpected Split Completion
19 RWC 0 0 = No unexpected Split Completion has been received.
1 = An unexpected Split Completion has been received.
Split Completion Discarded.
18 RWC 0 0 = No Split Completion has been discarded.
1 = A Split Completion has been discarded.
17
R
1 1 = The device’s maximum clock frequency is 133 MHz.
16
R
0 0 = The bus is 32 bits wide.
Bus Number.
Each time the function is addressed by a Configuration Write transaction, it
15:8 R FFh
will update the register with the contents of AD[7:0] of the attribute phase of
the Configuration Write.
Device Number.
Each time the function is addressed by a Configuration Write transaction, it
7:3
R 1Fh
will update the register with the contents of AD[15:11] of the attribute phase
of the Configuration Write.
2:0
R
000 Function Number
6.3 Host Registers definition:
( IOG = global, pointed by PCI Base Address Reg0 )
( IO01 = channel0&1, pointed by PCI Base Address Reg1 )
( IO23 = channel2&3, pointed by PCI Base Address Reg2, Reserved )
( IO45 = channel4&5, pointed by PCI Base Address Reg3, Reserved )
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1/20/2009