XRS10L620 Datasheet, PDF (30/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

Bit(s) R/W default Symbol
XRS10L620 Rev 1.00
Description
31:20 R
0h
Reserved
19:16 R
0h
15:12 R
0h
11:08 RW 0h
07:04 RW 0h
03:00 RW 0h
PMP
SPM
IPM
SPD
DET
Port Multiplier Port: not used by AHCI
Select power management, not used by AHCI
Use PxCMD.ICC instead
Indicates which power states are not allowed.
0h : No restrictions
1h : Disable transition to Partial state
2h : Disable transition to Slumber state
3h : Disable transition to both Partial and Slumber state
All other values reserved
Indicates the highest allowable speed :
0h : No speed restriction
1h : Limit speed negotiation to Gen 1
2h : Limit fastest speed negotiation to Gen 2
All other values reserved
Control HBA’s device detection and initialization.
0h : No action requested
1h : Perform initialization sequence like a hard reset.
COMRESET is transmitted continuously until software
change the field to 0h
4h : Disable the SATA interface and put Phy in offline mode
All other values reserved
This field may only be modified when PxXMD.ST is ‘0’.
Reg_130H (IO01+30h) : P0SERR (SCR1 : SError)
Bit(s) R/W default Symbol
Description
31:16 RWC 0000h DIAG Diagnostics
31:27 R
0h
26 RWC 0
25 RWC 0
24 RWC 0
23 RWC 0
22 RWC 0
21 RWC 0
20 RWC 0
19 RWC 0
18 RWC 0
17 RWC 0
16 RWC 0
15:00 RWC 0000h
15:12 R
0h
Reserved
Exchanged:
X 1=COMINIT(as Host) or COMRESET(as Device) received
This bit is reflected in the P0IS.PCS bit
F ^{Unknown FIS type received, include H2D and BIST FIS.}
T ^{Transport state transition error}
S ^{Link sequence error}
H
Handshake error:
R_ERR received, result from CRC, disparity, or 8b/10b error
C ^{CRC error}
D ^{Disparity error: not used by AHCI}
B ^{10b to 8b decode error}
W ^{COMWAKE signal was detected by the Phy}
I ^{Phy internal error}
N
PhyRdy changed:
This bit is reflected in P0IS.PRCS bit
ERR Error
Reserved
29
1/20/2009