XRS10L620 Datasheet, PDF (35/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

0 RW 0
PHYCTRLEN
XRS10L620 Rev 1.00
Set 1 to control TXrate, RXrate, Slumber, Partial
function
Reg_154H (IO01+54h): P0PLLTEST
** P1PLLTEST(IO01+D4h) is reserved, not available.
Bit(s) R/W Default
31:29 RW 000
28:26 RW 111
25 RW 0
Symbol
PLLTESTSEL
VFRSEL
PDPLL
Description
Select different PLL test mode
000= Test mode disabled 100= Bandgap voltage
001= Vcoin voltage
101= Charge pump
current source
010= Ground voltage
110= Charge pump
current sink
011= Vddreg voltage
111= VCO free running
Select Vcoin free running voltage
111 = 1.5V
011 = 1.0V
110 = 1.4V
010 = 0.9V
101 = 1.3V
001 = 0.7V
100 = 1.2V
000 = 0.5V
1 = Power down PLL
0 = Normal operation
24
R
1
LOCKDET ^{1 = PLL is locked}
0 = PLL is not locked
23:21 RW 000
20 RW 0
19:08 R
0
INDSEL
BYPASSLD
3 bits to select one of the signals below as
‘COM_DET0’ name shown in Reg_50H bit [19:16]
000 = COMDET0/CMMDETLH0
100 = COMSAS
001 = PRBSOK/PRBSOKLL
101 =SQULCH
010 = COMINIT
110 = reserved
011 = COMWAKE
100 = reserved
Bypass LOCKDET
1=POR_DG does not wait for LOCKDET
(POR_DG=POR when BYPASSLD=1)
0=POR_DG waits for LOCKDET
Reserved
7:6 RW 0
GIO3_SEL ^{GIO3_SEL[5:4], see also Reg_150H bit[31:28]}
5:4 RW 0
GIO2_SEL ^{GIO2_SEL[5:4], see also Reg_150H bit[27:24]}
3:2 RW 0
GIO1_SEL ^{GIO1_SEL[5:4], see also Reg_150H bit[23:20]}
1:0 RW 0
Reserved
Reg_158H (IO01+58h) : P0TxTEST
**bit [15:6] of P1TxTEST (IO01+D8h) are reserved
Bit(s) R/W Default
31 RW 0
Symbol
PARTIAL
Description
Power down TX and RX in Partial mode
1 = Power down
0 = No power down
Read value is from SATA return value
34
1/20/2009