XRS10L620 Datasheet, PDF (17/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

30:02 R
0
01 RW 0
00 RW1 0
XRS10L620 Rev 1.00
Reserved
Interrupt Enable
IE
0 = INTA# disabled for all interrupt from all ports
1 = INTA# enabled, if CFGM+4 bit10 =0 also
HBA internal reset, issued by SW and auto-cleared when reset
completed. SW should set‘1’once for power on initialization.
HR
If Reg_000H bit 27(SSS)=0, COMRESET issued to all ports.
If SSS=1, no COMRESET issued, SW need to spin-up each port
after the reset has completed.
The bit is self-cleared after reset action completed
Reg_008H (IOG+08h) : Interrupt Status Register (IS)
Bit(s)
31
30
29
28:09
08
07:02
01:00
R/W default
R
0
RWC 0
RWC 0
R
0
R
0
R
0
R 00b
Symbol
Description
IFS
Interrupt flag when as I2C slave, means one byte received
completed via I2C. Cleared when Reg_0B0H RXRS is read out
Interrupt flag when as I2C master, means one byte transfer
IFM completed via I2C. The interrupt is cleared as below :
Master receive : Read out Reg_0B0H RXRM.
Timer IRQ flag, 1=timer up
Set 1 will clear this flag and timer IRQ signal (INTA#)
Reserved to 0
IDEPS
Latched IDE IRQ flag, reflect the Reg_090H bit 18 when
Reg_090H bit 11 = 1
Reserved to 0
If set, the corresponding bit map port has at least an interrupt flag
IPS in P0IS, P1IS, and their P0IE, P1IE are enabled respectively.
Each bit is cleared when all flags in respective PxIS are cleared
Reg_00CH (IOG+0Ch): Ports Implemented
Bit(s) R/W default Symbol
Description
31:02 R
0
01:00 R 11b
=1, the bit significant port is available.
PI
=0, the bit significant port is not available
Reg_010H (IOG+10h) : AHCI Version (VS)
Bit(s)
31:16
15:00
R/W default
R 0001h
R 0000h
Symbol
MJR Major version is ‘1’
MNR Minor version is‘0’
Description
Reg_014H to Reg_07FH are reserved.
Reg_080H to Reg_087H (IOG+80h to 87h) :
Reg_80h to 87h are mapped to standard Parallel IDE port 0 to port7
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1/20/2009