XRS10L620 Datasheet, PDF (22/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

16 RW 0
15:13 R
0
12 RW 0
11 RW 0
10 R/W 0
09 RW 0
08 RW 0
07
R
0
06 RW 0
05 RW 0
04 RW 0
03 RW 0
02 RW 1
01 RW 1
00
R
0
XRS10L620 Rev 1.00
1=Enable PIOROM and also disable IDE function
RA[15:2] output are controlled by bit [15:2] of this register
RA[1:0] are auto-generated by chip
Reserved
1= enable UDMA150, when Reg_094H is also set to UDMA
mode 6 on that channel.
Test only. 1= delayed write strobe
Test only, set 1 to disable DAC
1 to issue DAC in every Memory access command, test only.
0: Rolling PCI arbitration on all channels
1: Fixed PCI retry arbitration on all channels
M66EN pin value
1 : Enable periodical issuing COMRESET on SATA channels
when their PHY are not ready
1 : For PCIX, forced Memory Write command instead of Memory
Write Block command
Reserved
1 : Disable Write SubSystem ID
1 : Enable PCI burst
1 : Enable PCI Memory Read Multiple
Reserved for PCI(X) 64 bit transfer
Reg_0ACH (IOG+ACh) : Timer Control
Bit(s) R/W default Symbol
Description
31:24 R
0
Reserved
23,22 R
00
Test only, Mem1 result, ‘11’= good, other values= error
21:20 R
00
Test only, Mem0 result, ‘11’= good, other values= error
18 RW1 0
TSTM1 Test only. Start to test Mem1
17 RW1 0
TSTM0 Test only. Start to test Mem0
16 RW 0
1 : Enable timer IRQ as INTA# signal
15 RW1 0
‘1’= start timer. The bit is auto-cleared when timer counts to 0
14:0 RW 0
15 bit timer count, in unit of 4 ms.
Auto decrement to 0, when timer starts.
Reg_0B0H (IOG+B0h) : I2C Bus Control
Bit(s) R/W default Symbol
Description
21
1/20/2009