XRS10L620 Datasheet, PDF (26/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

04:00
00000
04
R
0
03
R
0
02 RWC 0
01 RWC 0
00 RWC 0
If MultiPM bit (Reg_174H bit 1)=0,
XRS10L620 Rev 1.00
bit 4 and bit[2:0] fields are available for all PM#0 to #15
If MultiPM bit (Reg_174H bit 1)=1,
bit 4 and bit[2:0] fields are dedicated for PM#0 only
Unknown FIS interrupt, when the FIS is copied to memory
UFS
This bit is cleared by clearing PxSERR.DIAG..F bit
‘OR’ed flag of 40 bits of this register bit[16:9] and
SDBS
Reg_144h[31:0] about Set Device Bits FIS interrupts
DMA setup FIS interrupt : This FIS is received with ‘I’bit set and
DSS
has been copied into system memory
PIO setup FIS interrupt : This FIS is received with ‘I’ bit set, it and
PSS
its related data are all transferred
D2H register FIS interrupt : This FIS is received with ‘I’ bit set
DHRS
and has been copied into system memory
Reg_114H (IO01+14h) : P0IE, interrupt enable of second layer
First layer enable are the CFGM+4 bit 10 and GHC.IE bit
Bit(s) R/W default Symbol
Description
31 RW 0
CPDE If set, INTA# issued when P0IS.CPDS is set
30 RW 0
TFEE If set, INTA# issued when P0IS.TFES is set
29 RW 0
HBFE If set, INTA# issued when P0IS.HBFS is set
28 RW 0
HBDE If set, INTA# issued when P0IS.HBDS is set
27 RW 0
IFE If set, INTA# issued when P0IS.IFS is set
26 RW 0
INFE If set, INTA# issued when P0IS.INFS is set
25
R
0
Reserved
24 RW 0
OFE If set, INTA# issued when P0IS.OFS is set
23 RW 0
IPME If set, INTA# issued when P0IS.IPMS is set
22 RW 0
PRCE If set, INTA# issued when P0IS.PRCS is set (“N” bit)
21:09 R
0
Reserved
08 RW
0
NOTIE If set, INTA# issued when P0IS.NOTIS is set.
07 RW 0
DIE If set, INTA# issued when P0IS.DIS is set
06 RW 0
PCE If set, INTA# issued when P0IS.PCS is set (“X” bit)
05 RW 0
DPE If set, INTA# issued when P0IS.DPS is set (data completed)
04 RW 0
UFE If set, INTA# issued when P0IS.UFS is set (Unknown FIS)
03 RW 0
SDBE If set, INTA# issued when P0IS.SDBS is set
02 RW 0
DSE If set, INTA# issued when P0IS.DSS is set
25
1/20/2009