XRS10L620 Datasheet, PDF (21/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

29:28 RW 00
27:26 RW 00
25:24 RW 00
23:21 RW 000
20 RW 0
19:17 R
16
R
0
15 RW 0
14:01 R
0
00 RW 0
Function switch for GIO2 pin
XRS10L620 Rev 1.00
00 = normal function, as SDA
01 = output user defined bit(bit22) to GIO2
10 = output one SATA channel debug signal to GIO2, see
Reg_150H and Reg_1D0H
11 = output disabled, pure input mode
Set 1 to negate other share pins function (like SCL, SDA, LED1Z,
LED0Z), and dedicated as GIO pin(s)
Function switch for GIO1 pin
00 = normal function, as LED1#
01 = output user defined bit(bit21) to GIO1
10 = output one SATA channel debug signal to GIO1, see
Reg_150H and Reg_1D0H
11 = output disabled, pure input mode
Set 1 to negate other share pins function (like SCL, SDA, LED1Z,
LED0Z), and dedicated as GIO pin(s)
Reserved
User defined output value of GIO[3:1] pins, 1 to output high
Available if modes in bit[31:26] are enabled respectively
Reserved
GIO[3:1] pins input value respectively
Available if modes in bit[31:26] are switched to input mode
Reserved
1=GIO3 pin always output 1KHz signal when bit[31:30]= ‘01’
Reserved
Switch one SATA channel for output debug signals to GIO pin
0 = SATA channel 0
1 = SATA channel 1
Reg_0A8H (IOG+A8h) : PCI Bus Control and ROM Address
Bit(s) R/W default Symbol
Description
The corresponding RA[15:2] pins value, set 0/1 will output
31:18 RW 0
low/high, available if bit16(PIOROM) is enabled to ‘1’.
Reading of the bits reflect the real pins value.
17
R
0
Reserved
20
1/20/2009