XRS10L620 Datasheet, PDF (31/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

11 RWC 0
10 RWC 0
9 RWC 0
8 RWC 0
7:2
R
0h
1 RWC 0
0 RWC 0
XRS10L620 Rev 1.00
E
Internal error:
Master or Target abort occurred in the PCI bus
P ^{Protocol error: a violation of SATA protocol}
C ^{Persistent communication error}
T
Transient data integrity error: A data integrity error that was not
recovered by the interface
Reserved
M
Recovered communication error:
Communication was temporarily lost between host and device.
Recovered data integrity error: A data integrity error occurred that
I was recovered by a retry operation.
Reg_134H (IO01+34h) : P0SACT (SCR3 : SActive)
Bit(s)
31:00
R/W default
RW1 0h
Symbol
Description
Device status: used for FPDMA queuing operation prior to setting
DS ^{the PxCI.CI bit in the same command slot number.}
This field is clear via the Set Device Bits FIS, not by software.
Reg_138H (IO01+38h) : P0CI, Port0 command issue
Bit(s)
31:00
R/W default
RW1 0h
Symbol
Description
Set by software and cleared by hardware.
CI
Indicate that a command has been built for a command slot
number. Cleared when the HBA receives a FIS with BSY, DRQ,
and ERR bits cleared.
Reg_13CH (IO01+3Ch) : P0NOTIF (SCR4)
Bit(s) R/W default Symbol
Description
31:28 R
Reserved
0h
CLRPMP
27:24 RW 0h CLRPMP ^{The PM number for Reg_140H .CICLR to be cleared}
23:16 R
0h CLRPMP ^Reserved
15:00 RWC 0h
NOTIF
Bit indication of Port Multiplier #15 to #0
‘1’=this PM# receive a SetDevBits FIS with the N bit set to 1.
The bit is cleared by SW writing ‘1’, but not cleared due to a
COMRESET
Reg_140H (IO01+40h) : P0CICLR, Clear Port0 CI
Bit(s) R/W default Symbol
Description
30
1/20/2009