XRS10L620 Datasheet, PDF (13/49 Pages) Exar Corporation – PCI-X to 2-SATA/1-PATA Host Controller

14-17 RW
18-1B RW
1C-1F RW
20-23 RW
24-27 RW
28-2B R
Base Addr Reg1
Base Addr Reg2
Base Addr Reg3
Base Addr Reg4
Base Addr Reg5
Card CIS Pointer
XRS10L620 Rev 1.00
bit0 : fixed to 1
bit[7:1] : fixed to 0
other bits are read/writable
IO address of SATA channel 0 & 1 registers, length 256
bytes
bit0 : fixed to 1
bit[7:1] : fixed to 0
other bits are read/writable
IO address reserved for test, length 256 bytes
bit0 : fixed to 1
bit[7:1] : fixed to 0
other bits are read/writable
IO address reserved for test, length 256 bytes
bit0 : fixed to 1
bit[7:1] : fixed to 0
other bits are read/writable
IO address reserved for test, length 256 bytes
bit0 : fixed to 1
bit[7:1] : fixed to 0
other bits are read/writable
MEM address of Global and all SATA channels registers,
length 1280 bytes. The Memory accessed registers are
the same as those mapped by Base Addr [4:0].
bit[11:0] : fixed to 0, in 4KB range
other bits are read/writable
00000000h
2C-2F R/W Subsystem Vendor ID ^{Default are same as Vendor ID and Device ID}
Subsystem Device ID
30-33
34
R/W Expansion ROM Base ^{bit0 : read/writable, set 1 to enanble the ROM}
bit[15:1] : fixed to 0
Address
bit[31:16] : read/writable
R
Cap_Pointer
(40h) point to power management link list
35-3B R
Reserved
00h
3C RW
Interrupt line
00h
3D
R
Interrupt pin
01h, INTA#
3E
R
Min_GNT
08h, specify a burst period in 250ns unit
3F
R
Max_LAT
0Dh, specify how often the device needs to gain access
the PCI
bus in 250ns unit
40 to 47 RW
PCI power
Refer to section (2.1)
management registers
48 to 4F RW PCI-X Capabilities List Refer to section (2.2)
Item
6.1.1 PCI Power Management Registers :
CFGM+40h to 47h : 8 bytes PCI power management registers
CFGM+40h (R): Capability ID, default 01H
CFGM+41h (R): Next Item Pointer, default 48H
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1/20/2009