MC3630 Datasheet, PDF(45/83 Page)

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MC3630 Datasheet, PDF (45/83 Pages) –

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MC3630 3-Axis Accelerometer

Preliminary Datasheet

SPI_STAT_EN

SPI 4-wire mode SPI status token.

During the first SPI write cycle from the host, enabling this

bit will cause the interface to send out system status

information on the DOUT_A1 pin without requiring a

separate read cycle. See 5.11 SPI Status Option.

0: No SPI status flags are shifted out (default)

1: SPI status flags are shifted out on the first byte of all 4-

wire SPI transactions (SPI 3-wire and I2C modes are not

supported, so no effect will be seen in those modes).

FIFO_STAT_EN FIFO status token enable. This bit enables a 4-bit FIFO

status token to be appended to the top 4 bits of the Z-

channel data in every FIFO read cycle. This feature works

in I2C mode and both SPI modes. When enabled, the

format of the FIFO status token is:

0: FIFO status feature is disabled, Z channel FIFO data is

not overwritten with FIFO status information. (default)

1: FIFO status feature is enabled. When the resolution is

less than 14-bits, the top 4-bits of 16-bit Z channel FIFO

data are replaced with FIFO status information:

{[INT_PEND, FIFO_TH, FIFO_FULL, FIFO_EMPTY],

Z[11:0]}

When the resolution is 14-bits or above, the bottom 4-bits

are replaced:

{[ Z[15:4], INT_PEND, FIFO_TH, FIFO_FULL,

FIFO_EMPTY]}

I2CINT_WRCLRE Clear interrupts on register 0x09 write in I2C mode. The

default method of interrupt clearing is reading register 0x09,

the INT_STATUS or STATUS_2 register. When this bit is

enabled, reads to register 0x09 do not clear pending

interrupts. SW must write to register 0x09 (contents do not

matter) to clear any pending interrupts.

NOTE: In SPI mode this bit has no effect; SPI interrupt

clearing requires a write to register 0x09; reads are not

supported.

0: In I2C mode, interrupts are cleared when reading register

0x09 (default)

1: if I2C_EN is â1â, then interrupts are cleared when writing

to register 0x09. Otherwise I2C reads to register 0x09 will

still clear pending interrupts.

mCube Proprietary

APS-048-0047v1.2

45 / 83

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