MC3630 Datasheet, PDF (40/83 Pages) –

MC3630 3-Axis Accelerometer
Preliminary Datasheet
(0x09) Status Register 2
This register reports the state of the interrupts (‘0’ means not pending; ‘1’ means pending). A
bit in this register will only be set if the corresponding interrupt enable is set to ‘1’ in (0x17)
Interrupt Control Register. Interrupts can be cleared in the following ways using (0x0E)
Feature Register 2 bit 4:
Interface
I2C clearing method (default)
I2C clearing method (optional)
SPI clearing method
Method
Read Register 0x09
Write Register 0x09
Write Register 0x09
Addr Name
7
6
5
Bit
4
3
POR
2
1
0
Value R/W
0x09 STATUS_2 INT_ INT_FIFO_ INT_FIFO_ INT_FIFO_ INT_ACQ INT_WAKE RESV RESV 00000000 RO
SWAKE THRESH
FULL
EMPTY
Bit
[1:0]
2
Name
Reserved
INT_WAKE
3
INT_ACQ
4
INT_FIFO_EMPTY
Description
Reserved.
This interrupt will transition when the accelerometer
automatically moves from SNIFF to CWAKE. Once
cleared, another SNIFF to CWAKE event must take
place to retrigger it.
This interrupt will transition when a new sample is
acquired. This flag stays high upon the first sample
acquired and will not rearm unless cleared. Only
active in CWAKE and TRIG modes.
This interrupt will transition when the FIFO is empty.
This flag stays high upon the first empty condition
and will not rearm unless cleared. The FIFO empty
condition must be negated (e.g. the FIFO must
become ‘not’ empty), and then empty again for the
INT_FIFO_EMPTY flag to retrigger.
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APS-048-0047v1.2
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