MC3630 Datasheet, PDF (44/83 Pages) –

MC3630 3-Axis Accelerometer
Preliminary Datasheet
(0x0E) Feature Register 2
This register allows selection of various features for the FIFO, external trigger input, method of
interrupt clearing and burst address wrapping.
Bit
POR
Addr Name
7
6
5
4
3
2
1
0
Value R/W
0x0E FREG_2 EXT_
EXT_
FIFO_ I2CINT_ FIFO_
SPI_
FIFO_ WRAPA 0000000 RO
TRIG_EN TRIG_POL STREAM WRCLRE STAT_EN STAT_EN BURST
0
Bit
Name
0
WRAPA
1
FIFO_BURST
Description
Burst read address wrap control. This bit determines the
“roll-back” or wrap address during burst reads. This bit
works in I2C mode and both SPI modes.
0: Burst read cycle address wrap address is 0x07, counter
automatically returns to 0x02. (default)
1: Burst read cycle address wrap address is 0x09, counter
automatically returns to 0x02. This setting allows for status
registers 0x08 and 0x09 to be included in the burst read.
FIFO burst feature. This bit enables address increment
logic which allows extended atomic burst reads of the FIFO
greater than the standard 6-byte (3x16 bits) atomic burst
read of XYZ data. This bit works in I2C mode and both SPI
modes.
0: FIFO burst read cycles are 6-bytes in length, 0x02 to
0x07 per read cycle transaction (default).
1: FIFO burst read cycle can be any number of 6-byte
reads, up to 32 x 6 bytes (i.e. the entire FIFO contents can
be read).
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