MC3630 Datasheet, PDF (29/83 Pages) –

MC3630 3-Axis Accelerometer
Preliminary Datasheet
SPI 3-Wire Mode
SPI 3-wire mode is disabled by default. To enable 3-wire mode, the first write to the device
should immediately enable this feature in register (0x0D) Feature Register 1. In 3-wire mode
the pins DOUT_A1 and DIN_SDA must be connected on the PCB. Anytime there is a reset to
the device, a POR event, or a power cycle the SPI 3-wire configuration will reset to 4-wire
mode.
SPI Protocol
The general protocol for the SPI interface is shown in the figures below. The falling edge of
CSN initiates the start of the SPI bus cycle. The maximum SPI clock speed is 4Mhz and the
timing scheme follows clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. The first byte of
the transaction is the command/address byte. Because the register address space is 64
locations, a total of 6 address bits are required for each SPI bus cycle. During clock ‘1’, the
R/W# bit is set to ‘0’ for a write cycle or ‘1’ for a read cycle.
The interface supports 2 types of addressing: 1-byte (typically used) and 2-byte (to support
legacy hardware). In the case of 2-byte addressing, the bits occurring during clocks 2 and 9-16
must be driven to ‘0’ for the address to be correctly decoded. Each read or write transaction
always requires a minimum of 16 or 24 cycles of the SCK_SCL pin.
When the SPI master is writing data, data may change when the clock is low, and must be
stable on the clock rising edge. Similarly, output data written to the SPI master is shifted out on
the falling edge of clock and can be latched by the master on the rising edge of the clock.
Serial data in or out of the device is always MSB first.
CSN
SCK_SCL
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DIN_SDA
R/W 1
A5 A4 A3 A2 A1 A0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
DOUT_A1
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Figure 14. General SPI Protocol, 1-Byte Address
CSN
SCK_SCL
DIN_SDA
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
R/W 0
A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
DOUT_A1
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Figure 15. General SPI Protocol, 2-Byte Address (legacy)
NOTE: Either 1-byte or 2-byte addressing may be used for any SPI transaction, although
for simplicity, the remaining timing diagrams show only 1-byte addressing.
SPI Register Write Cycle - Single
A single register write consists of a 16-clock transaction. As described above, the first bit is set
to ‘0’ indicating a register write followed by the register address.
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