MC3630 Datasheet, PDF (30/83 Pages) –

MC3630 3-Axis Accelerometer
Preliminary Datasheet
CSN
SCK_SCL
DIN_SDA
DOUT_A1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
0
1
A5 A4 A3 A2 A1 A0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
Figure 16. SPI Register Write Cycle - Single
SPI Register Write Cycle - Burst
A burst (multi-byte) register write cycle uses the address specified at the beginning of the
transaction as the starting register address. Internally the address will auto-increment to the
next consecutive address for each additional byte (8-clocks) of data written beyond clock 8.
NOTE: See (0x0E) Feature Register 2 for address wrap details.
CSN
SCK_SCL
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DIN_SDA
DOUT_A1
0
1
A5 A4 A3 A2 A1 A0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8
Data for register N
Data for register N+1
Figure 17.SPI Register Write Cycle - Burst (2-register burst example)
SPI Register Read Cycle - Single
A single register read consists of a 16-clock transaction. As described above, the first bit is set
to ‘1’ indicating a register read followed by the register address.
CSN
SCK_SCL
DIN_SDA
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
1
A5 A4 A3 A2 A1 A0
DOUT_A1
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Figure 18. SPI Register Read Cycle - Single
SPI Register Read Cycle - Burst
A burst (multi-byte) register read cycle uses the address specified at the beginning of the
transaction as the starting register address. Internally the address will auto-increment to the
next consecutive address for each additional byte (8-clocks) of data read beyond clock 8.
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APS-048-0047v1.2
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