MC3630 Datasheet, PDF (31/83 Pages) –

MC3630 3-Axis Accelerometer
Preliminary Datasheet
NOTE: See (0x0E) Feature Register 2 for address wrap details.
CSN
SCK_SCL
DIN_SDA
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
1
A5 A4 A3 A2 A1 A0
DOUT_A1
DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8
Data from register N
Data from register N+1
Figure 19. SPI Register Read Cycle - Burst (2 register burst example)
SPI Status Option
The device supports an optional SPI status feature, only in SPI 4-wire mode. This feature is
enabled in register (0x0E) Feature Register 2. During the first 6-bits of any SPI transaction
(immediately after the falling edge of CSN), the DOUT_A1 pin will output six status bits related
to the device. Following the 6th clock cycle, the device will float the DOUT_A1 pin before a
possible read cycle begins. The status bits sent are shown below:
Bit 7
(First Out)
Bit6
Bit 0
Bit5
Bit 4
Bit 3
Bit 2
Bit 1
(Last Out)
INT_PEND FIFO_THRESH FIFO_FULL FIFO_EMPTY NEW_DATA
WAKE
0
0
CSN
SCK_SCL
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DIN_SDA
R/W 1ADR A5 A4 A3 A2 A1 A0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
DOUT_A1
INTP FTH FULL MTY NEW WAKE 0
0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Any SPI Transaction
INT_PEND
FIFO_THRESH
FIFO_FULL
WAKE
NEW_DATA
FIFO_EMPTY
Figure 20. SPI Status bits
mCube Proprietary
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APS-048-0047v1.2
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