MC3630 Datasheet, PDF (42/83 Pages) –

MC3630 3-Axis Accelerometer
Preliminary Datasheet
(0x0D) Feature Register 1
This register is used to select the interface mode as well as the operation style of the FIFO and
interrupt in SWAKE mode.
NOTE: Software must set only one of the bits SPI_EN or I2C_EN or SPI3_EN in register
0x0D to ‘1’, depending upon if the I2C or SPI 4 wire or SPI 3 wire interface will be used
for external communications. No data will appear in XOUT, YOUT and ZOUT registers if
both the I2C_EN bit and SPI_EN bit and SPI3_EN bit are set to 0 (default).
Bit
Addr
Name
7
6
5
4
3
2
0x0D FREG_1 SPI_EN I2C_EN SPI3_EN INTSC_EN FREEZE
0
POR
1
0
Value R/W
0
0
00000000 RO
Bit
[2:0]
3
Name
<Must write ‘000’>
FREEZE
4
INTSC_EN
Description
Software must always write ‘000’ to these 3 bits
This bit is designed to be used with “FIFO stream
mode” (register 0x0E bit 5) where the FIFO is
configured to continuously capture new samples and
flush the oldest after reaching a FIFO full state.
0: FIFO operates in standard mode, does not stop
capturing data in SWAKE interrupt (default).
1: FIFO stops capturing on SWAKE interrupt,
software can examine the conditions which
generated the SWAKE event.
Once an SWAKE interrupt is generated, the SNIFF
block stops processing new events until cleared.
Enabling this bit allows the SNIFF block to be reset at
the same time the INT_SWAKE interrupt is cleared.
0: Do not re-arm SNIFF block following a SWAKE
event (requires the SNIFF block to be reset by exiting
SWAKE mode). (default)
1: Clearing the SWAKE interrupt clears and rearms
the SNIFF block for subsequent detections (device
may stay in SWAKE mode and continuing processing
subsequent SWAKE events once interrupt is
cleared).
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