MC3630 Datasheet, PDF (33/83 Pages) –

MC3630 3-Axis Accelerometer
Preliminary Datasheet
Register Summary
Addr
Nam e
De s cription
0x00 EXT_STAT_1 Extended Status 1
0x01 EXT_STAT_2 Extended Status 2
0x02 XOUT_LSB
XOUT_LSB
Bit 7
Bit 6
Bit 5
RESV
SNIFF_
DETECT
XOUT[7]
RESV
SNIFF_EN
XOUT[6]
RESV
OTP_
BUSY
XOUT[5]
Bit 4
RESV
RESV
XOUT[4]
Bit 3
I2C_A D0
RESV
XOUT[3]
Bit 2
RESV
RESV
XOUT[2]
Bit 1
RESV
PD_CLK_
STA T
XOUT[1]
Bit 0
RESV
OV R_
DA TA
XOUT[0]
POR _R/W4
V alue
0x00
R
0x04
R
0x00
R
0x03 XOUT_MSB XOUT_MSB
XOUT[15] XOUT[14] XOUT[13] XOUT[12] XOUT[11] XOUT[10] XOUT[9] XOUT[8] 0x00
R
0x04 YOUT_LSB
Y OUT_LSB
YOUT[7] YOUT[6] YOUT[5] YOUT[4] YOUT[3] YOUT[2] YOUT[1] YOUT[0] 0x00
R
0x05 YOUT_MSB YOUT_MSB
YOUT[15] YOUT[14] YOUT[13] YOUT[12] YOUT[11] YOUT[10] YOUT[9] YOUT[8] 0x00
R
0x06 ZOUT_LSB
ZOUT_LSB
ZOUT[7] ZOUT[6] ZOUT[5] ZOUT[4] ZOUT[3] ZOUT[2] ZOUT[1] ZOUT[0] 0x00
R
0x07 ZOUT_MSB
0x08 STATUS_1
0x09 STATUS_2
0x0A – 0x0C
ZOUT_MSB
Status 1
Status 2
ZOUT[15] ZOUT[14] ZOUT[13] ZOUT[12] ZOUT[11] ZOUT[10] ZOUT[9] ZOUT[8] 0x00
R
INT_PEND
FIFO_ _{FIFO_FULL} FIFO_
THRESH
EMPTY
NEW_
MODE[2] MODE[1] MODE[0] 0x00
R
DA TA
INT_
INT_FIFO_ INT_FIFO_ INT_FIFO_ _{INT_ACQ INT_WAKE}
SWAKE THRESH
FULL
EMPTY
RESV
RESV
0x00
R
RESERV ED
0x0D FREG_1
0x0E FREG_2
0x0F INIT_1
0x10 MODE_C
0x11 RATE_1
0x12 SNIFF_C
0x13 SNIFFTH_C
0x14 SNIFFCF_C
0x15 RANGE_C
0x16 FIFO_C
0x17 INTR_C
0x18 CHIP_ID
Feature 1
SPI_EN
I2C_EN SPI3_EN INTSC_EN FREEZE
0
0
0
0x00
Feature 2
EXT_
TRIG_EN
EXT_
TRIG_POL
FIFO_
STREAM
I2CINT_
WRCLRE
FIFO_
STAT_EN
SPI_
STAT_EN
FIFO_
BURST
WRAPA
Initialization 1
0
1
0
0
0
0
1
0
Mode Control
Rate 1
Snif f Control
Snif f Threshold
Control
Snif f Conf iguration
Range Resolution
Control
FIFO Control
Interrupt Control
TRIG_
Z_AXIS_ Y_AXIS_ X_AXIS_
CMD
PD
PD
PD
RESV
MAN_SEL MAN_SEL MAN_SEL
[2]
[1]
[0]
STB_RATE STB_RATE STB_RATE
0
[2]
[1]
[0]
SNIFF_
SNIFF_
SNIFF_
SNIFF_
MODE AND_OR
TH[5]
TH[4]
SNIFF_
SNIFF_
SNIFF_
SNIFF_
RESET
MUX[2]
MUX[1]
MUX[0]
RESV
WR[3]
SNIFF_SR
[3]
SNIFF_
TH[3]
SNIFF_
CNTEN
MCTRL[2]
WR[2]
SNIFF_SR
[2]
SNIFF_
TH[2]
SNIFF_
THA DR[2]
MCTRL[1]
WR[1]
SNIFF_SR
[1]
SNIFF_
TH[1]
SNIFF_
THA DR[1]
MCTRL[0]
WR[0]
SNIFF_SR
[0]
SNIFF_
TH[0]
SNIFF_
THA DR[0]
RESV RANGE [2] RANGE [1] RANGE [0] RESV
RES[2]
RES[1]
RES[0]
FIFO_
RESET
INT_
SWA KE
FIFO_EN
INT_FIFO_
THRESH
FIFO_
MODE
INT_FIFO_
FULL
FIFO_TH[4] FIFO_TH[3] FIFO_TH[2] FIFO_TH[1] FIFO_TH[0]
INT_FIFO_ _{INT_ACQ}
INT_
IA H
IPP
EMPTY
WA KE
0x00
(See
note)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Chip ID Register
0
1
1
1
0
0
0
1
0x71
W
W
WO
W
W
W
WS
W
W
W
R
R
0x19
RESERV ED
0x1A INIT_3
Initialization 3
0
0
0
0
0
0
0
0
0x00 RW
mCube Proprietary
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