GC4116 Datasheet, PDF (9/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
3.2 CHANNEL INPUT FORMAT
The input samples are 16 bits, either real or complex.
The samples are input to the chip either through the bit-serial
input ports, or through memory mapped control registers.
The channel data request signal (CHREQ) is output from the
chip to identify when the GC4116 is ready for another
complex input sample or pair of real samples.
3.2.1 Bit Serial Interface
The bit serial format consists of a data input pin (SIN), a
bit clock pin (SCK), and a frame strobe pin (SFS) for each of
the four channels (A,B,C and D), and a channel data request
pin (CHREQ) which is common to all channels.
The serial channel inputs can come directly from the
Four Channel Resampler by connecting the resampler’s
serial output ports to the channel’s serial input ports, and
connecting the CHREQ pin to the resampler’s RSTART pin.
The Resampler and its I/O interface is described in Section
3.7.
If the Resampler is not being used, then the Serial
Controller can be used to generate the proper serial clocks
and frame strobes fro the channel inputs. In this case
CHREQ is tied to SCSTART, and then SCCK and the SCFS
strobes are used to drive the serial clock and frame strobes
for both the channel inputs and the channel data source
(typically a DSP chip, FPGA, or ASIC).
DATA SHEET REV 1.0
The bit serial samples are always entered MSB first.
Complex values are entered I-half first followed by the Q-half.
Real values are entered as pairs of samples, with the first
sample in the I-half and the second sample in the Q-half. The
input accepts either pairs of 16 bit words each with its own
frame strobe (the unpacked mode), or as a single 32 bit
transfer with a single frame strobe (the packed mode). The
bit serial input formats are shown in Figure 4
Figure 4a shows the unpacked input mode (PACKED in
the input control register is low). The user provides a bit serial
clock (SCK), a frame strobe (SFS) and a data bit line (SIN).
The chip clocks SFS and SIN into the chip on the rising edge
of SCK (or falling edge if the SCK_POL bit in the input control
register is set). The user sends a 16 bit serial input word to
the GC4116 by setting SFS high (or low if SFS_POL in the
input control register is set) for one SCK clock cycle, and
then transmitting the data, MSB first, on the next 16 SCK
clocks. The SFS may remain high during the transfer, but
must go low for one SCK cycle before the next serial word is
sent. The serial sample is transferred to a parallel register on
the next SCK clock. Additional SCK clocks are acceptable
but are ignored. The data can be transmitted “back to back”
as shown in Figure 4b as long as the SFS signal toggles low
and then high as shown. If the PACKED control bit is high,
then the I and Q samples (or I0 then I1 for real data) are sent
as a single 32 bit word with only one SFS strobe as shown in
Figure 4c.:
SCK
SFS
SIN
SCK
SFS
SIN
SCK
SFS
SIN
T_SU
T_HD
(must go low before next transfer)
T_SU
T_HD
I15
I14
I13
I3
I2
I1
I0
(a) UNPACKED MODE
I15
I14
I13
I3
I2
I1
(b) 16 BIT MODE, BACK TO BACK TRANSFER
I0
Q15
(SFS occurs once at beginning of the 32 bit transfer)
I15
I14
I13
I3
I2
I1
(c) 32 BIT “PACKED” MODE
Figure 4. Serial Input Formats
I0
Q15
© 1999−2001 GRAYCHIP,INC.
-4-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice