GC4116 Datasheet, PDF (10/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
The GC4116 input interface sends a channel data
request strobe (CHREQ) when a new input sample is
required for the up-converter channels. The CHREQ strobe
is output from the chip every 4N clocks, where N is the
interpolation ratio in the CIC filter. The pulse width of the
CHREQ strobe is one CK period. The polarity of CHREQ is
user programmable. The CHREQ strobe is typically
connected to SCSTART of the serial request controller, or to
RSTART of the resampler (See Section 3.7.9). CHREQ can
also be used as an interrupt to an external device to tell it to
send another input sample. The GC4116 chip must receive
the last data bit at least one bit clock (SCK) period before the
next CHREQ strobe.
The frame sync can be sent up to 7 bit clocks before
CHREQ. This is normally used when the serial interface
timing is tight, i.e., the CHREQ rate is less than 34 SCK
cycles, so that there is not time between CHREQ strobes to
send SFS, then 32 bits and then have an SCK cycle before
the next CHREQ.
Very Important Note: The chip requires that SCK be
active when frame sync occurs, and be active for one cycle
after the last bit is sent. Serial data can be sent using only 32
SCK clocks per CHREQ period if the frame sync for the 16
bit I word (or the 32 bit I/Q word in the PACKED mode) is
coincident with the last bit of the previous transfer. The Serial
Controller block described in Section 3.8 can provide
appropriately timed frame strobes and serial clocks.
3.2.2 Memory Mapped Interfaced
Input samples can be entered into the chip using the
control interface. Addresses 16 through 31 on page 3 are the
input data registers. Note that these registers can be written
to in a DMA burst, 8 bits at a time. Note that some DMA
formats write samples most significant byte first. If this is the
case then the DMA should write from address 31 down to
address 16. The CHREQ strobe from the GC4116 chip
defines when the DMA transfer can start. The transfer must
DATA SHEET REV 1.0
be done before the next CHREQ strobe is received. See
global address 14 for handshake details.
3.3 THE UP-CONVERTERS
Each up-converter channel uses a two stage interpolate
by four filter and a 5 stage cascaded integrate-comb (CIC)
filter to increase the sample rate of the input data up to the
chip’s clock rate. An NCO and mixer circuit modulates the
signal up to the desired center frequency.
A block diagram of each up-convert channel is shown in
Figure 5. Each input sample is multiplied by an 8 bit 2’s
complement gain word. The gain adjustment is GAIN/128,
where the gain word (GAIN) ranges from -128 to +127. This
gives a 42 dB gain adjustment range. Setting G to zero clears
the channel input. A different gain can be specified for each
channel. The gain values are double buffered and may be
transferred to the active register on a sync. The transfer is
delayed so that the new values take effect on the same
sample for all channels. Gain is described in more detail in
Section 3.6.
After the gain has been applied, the input samples are
interpolated by a factor of 2 in a 63 tap filter with
programmable coefficients (PFIR). A typical use of the PFIR
is to implement matched (root-raised-cosine) transmit filters.
The PFIR will also, if desired, convert real input data to
single-sideband complex data. In this mode the PFIR does
not interpolate by a factor of 2. Instead it down-converts the
input data by F_S/4, where F_S is the input sample rate, and low
pass filters the result.
The second interpolate by 2 filter is a 31 tap
compensating filter (CFIR) which both interpolates by 2 and
pre-compensates for the droop associated with the CIC filter
that follows it.
The CIC filter interpolates by another factor of N=(8 to
1,448) to give an overall interpolation factor of 32 to 5,792
(16 to 2,896 in the real input mode).
I
FROM
INPUT
FORMATTER
Q
cosine
OUT
sine
TUNING
FREQUENCY
PHASE
OFFSET
NCO
Figure 5. The Up-converter Channel
© 1999−2001 GRAYCHIP,INC.
-5-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice