GC4116 Datasheet, PDF (20/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
pulse. In general, the lower 4 bits of SC_FRAME_CNT
should be non-zero.
The serial control supports both the packed and
unpacked serial modes, where the unpacked mode expects
a serial frame strobe for each 16 bit word of a complex pair,
and the packed mode expects a single frame strobe for the
32 bit complex pair.
The frame strobe in the packed mode (PACKED=1 and
SC_MODE=1, or RES_PACKED=1 and SC_MODE=0, in
addresses 16 and 17 of the IO Control page) may be
positioned in one of 15 delays, corresponding to
SC_FS_DELAY values of 0 through 14. In the unpacked
mode only the upper three bits of the counter are compared
with the upper 3 bits of the SC_FS_DELAY values. The lower
bit of the SC_FS_DELAY values must be zero. This means
that the values will match twice, outputting two frame
strobes, 16 bits apart.
If the input data is coming from four serial streams, so
that the four frame strobes should be sent at the same time,
then SCFRAME_CNT should be set to 17, and the four
SC_FS_DELAY values should be set to “1”. Larger values of
SC_FRAME_CNT can be used in this case in order to spread
out the RREQ periods.
If the data is coming from a single TDM bus, then
SCFSA (or SCSTART) can be sent to the data source to start
the TDM frame, and then SCFSB, SCFSC and SCFSD can
be delayed to identify the appropriate time slots in the TDM
bus.
When the serial controller is being used with the channel
inputs (not the resampler) and the upconvert interpolation
factor is 32 or 36, then the frame delays must be used to
delay the serial frames to start between 2 to 7 clocks before
the next CHREQ strobe. This is because of the requirement
that the serial transfer of 32 bit is completed 2 to 7 clocks
before the next CHREQ strobe (See Section 3.2.1). This
means that for an interpolation of 32 (the CIC interpolation
factor N is 8), SC_FRAME_CNT should be set to 39 and the
SC_FS_DELAY values should be “1”. For an interpolation of
36 (N=9) SC_FRAME_CNT should be 43. For larger
interpolation factors the default value of 17 can be used.
NOTE that if the serial clock is divided, then similar delay
values may need to be used in order to insure that the serial
frame is complete before the next CHREQ.
3.9 CLOCKING
The chip clock rate is equal to the output data rate which
can be up to 100 MHz. An internal clock doubler doubles the
DATA SHEET REV 1.0
clock rate so that the internal circuitry is clocked at twice the
data rate. The clock doubler requires 4-5 clocks to adapt to
the rate of the incoming clock during which time the reset
should be active. A gated clock, not uniform clock period
clock, is not suitable for this device above 40 MHz. A test
mode (ext_2xck) allows the use of an external double rate
clock (ck2x pin). This is intended for use in production test.
Please contact Graychip if further information on this mode
is needed.
3.10 POWER DOWN MODES
The chip has a power down and clock loss detect circuit.
This circuit detects if the clock is absent long enough to
cause dynamic storage nodes to lose state. If clock loss is
detected, an internal reset state is entered to force the
dynamic nodes to become static. The control registers are
not reset and will retain their values, but any data values
within the chip will be lost. When the clock returns to normal
the chip will automatically return to normal. In the reset state
the chip consumes only a small amount of standby power.
The user can select whether this circuit is in the automatic
clock-loss detect mode, is always on (power down mode), or
is disabled (the clock reset never kicks in) using the
DISABLE_CK_LOSS control bit in address 13 and the
GLOBAL_RESET control bit in address 5. The whole chip, or
individual down converter channels can be powered down.
Individual channels are powered down using the RESET_A,
B, C and D control bits in address 5.
3.11 SYNCHRONIZATION
Each GC4116 chip can be synchronized through the
use of one of two sync input signals, an internal one shot
sync generator, or a sync counter. The sync to each circuit
can also be set to be always on or always off. Each circuit
within the chip, such as the sine/cosine generators or the
interpolation control counter can be synchronized to one of
these sources. These syncs can also be output from the chip
so that multiple chips can be synchronized to the syncs
coming from a designated “master” GC4116 chip.
© 1999−2001 GRAYCHIP,INC.
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APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice