GC4116 Datasheet, PDF (44/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
RESAMPLER CONTROL PAGE 8 (continue)
ADDRESS 18: Filter Select Register, Suggested default = 0x00
BIT
0-1 LSB
2-3
4-5
6-7 MSB
TYPE
R/W
R/W
R/W
R/W
NAME
FILTER_SEL_0
FILTER_SEL_1
FILTER_SEL_2
FILTER_SEL_3
DESCRIPTION
The filter map for resampler channel 0. This select which of the NFILTER filters
to use for this channel. Must be less than or equal to NFILTER
The filter map for resampler channel 1.
The filter map for resampler channel 2.
The filter map for resampler channel 3.
ADDRESS 19: Final Shift Register, Suggested default = 0x14
BIT
0-3 LSB
4-5
6,7 (MSB
TYPE
R/W
R/W
R/W
NAME
FINAL_SHIFT
ROUND
Unused
DESCRIPTION
The final shift up applied to all resampler channels before rounding and
outputting. Legal values are 0-15.
Round the output to 12 (ROUND=0), 16 (ROUND=1), 20 bits (ROUND=2) or 24
bits (ROUND=3). Note, ROUND must be set to 1 (16 bits).
ADDRESS 20: Serial Map Register, Suggested default = 0xE4
BIT
0-1 LSB
2-3
4-5
6-7 MSB
TYPE
R/W
R/W
R/W
R/W
NAME
SERIAL_MAP_A
SERIAL_MAP_B
SERIAL_MAP_C
SERIAL_MAP_D
DESCRIPTION
The map for serial input A. This tells the hardware which resampler channel
serial input A should be directed to.
The map for serial input B.
The map for serial input C.
The map for serial input D.
This register maps resampler serial inputs to resampler channels. For most applications this will be a simple map of input A
to resampler channel 0, input B to resampler channel 1, etc. However, for two channel and one channel modes the mapping is
non-standard. The resampler input buffer requires that serial input D is always active, so in the single channel mode serial input
D must be mapped to resampler channel 0. This requires the serial map register to be set to 0x00. For two channels, serial inputs
C and D will be active and they should be mapped to resampler channels 0 and 1. This requires the serial map register to be set
to 0x40.
ADDRESS 21: Ratio Sync, Suggested default = 0x20
BIT
0-3 LSB
4-6
7 MSB
TYPE
R/W
R/W
R/W
NAME
TEST
RATIO_SYNC
Unused
DESCRIPTION
For Factory test purposes, must be set to zero.
Changes to the ratio map (address 23) are synchronized to this sync source.
The sync modes are: 0,1 and 5 are “never”, 2=SIA, 3=SIB, 4=OS, and 6,7 are
“always”.
When processing complex input signals partial results are computed in adjacent channels that must be summed together to
produce a meaningful result. This control bit informs the resampler to save the data presented to it’s input and add it to the next
sample presented (if the chip is properly set up this will be from the next channel). In this manner the real and imaginary portions
of the input are rejoined prior to resampling.
© 1999−2001 GRAYCHIP,INC.
- 39 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice