GC4116 Datasheet, PDF (32/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
ADDRESS 12: Channel Flush Register, suggested default = 0x55
BIT
0,1 LSB
2,3
4,5
6,7 MSB
TYPE
R/W
R/W
R/W
R/W
NAME
FLUSH_A[0:1]
FLUSH_B[0:1]
FLUSH_C[0:1]
FLUSH_D[0:1]
DESCRIPTION
The flush sync for channel A.
The flush sync for channel B.
The flush sync for channel C.
The flush sync for channel D.
This register controls flushing the four channels. Each channel is flushed when the selected sync occurs. Sync mode 1 is
SIA. The sync is selected according to Table 1 in Section 3.11.
Each channel needs to be flushed when the chip is being initialized or when the interpolation control is changed. The flush
lasts for 8N clocks after the sync occurs. The channel flush syncs will normally be left in a “never” mode. During diagnostics the
channels will need to be flushed at the beginning of each sync cycle.
ADDRESS 13: Miscellaneous Register, Set to zero on power up
BIT
0 LSB
1
2
3
TYPE
R/W
R/W
R/W
R/W
4
R/W
5
R/W
6
R/W
7
R/w
NAME
DISABLE_AUTO_FLUSH
MSB_INVERT
COMPLEX_OUT
EXT_2XCK
CK2X_TEST
DISABLE_CK_LOSS
FOUR_OUT _MODE
(GC4117 only)
OS_MODE
DESCRIPTION
The chip normally automatically flushes a channel if instability in the channel’s
CIC filter is detected. If this bit is set the auto flush feature is disabled.
Inverts the MSB of the output data (SUMO21) for use with offset binary DACs.
Should not be set for chips feeding the sumin port of another GC4116.
Complex output is generated with I followed by Q. Interpolation amount is 2N for
complex input and N for real input.
For test purposes an external 2x clock can be supplied. This control bit enables
its use. Normal use will set this bit to zero.
For test purposes the internally generated 2x clock can be routed to the soB pin
for test. Normal use will set this bit to zero.
The absence of a clock for extended times (1mS) can cause a current surge. An
internal circuit detects this condition prior to the current surge and puts the chip
into a reset state. This control bit disables this feature. Normal use will set this bit
to zero.
Puts the chip into the GC4117’s four separate output mode. Is only valid for the
208 ball GC4117 package. Must be set low for the 160 ball GC4116 package.
The ONE_SHOT signal is a level, not a pulse when this bit is set.
© 1999−2001 GRAYCHIP,INC.
- 27 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice