GC4116 Datasheet, PDF (39/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
5.7 I/O CONTROL PAGE (PAGE 5)
Page 5 controls the formatting and IO speed of channel and resampler inputs, resampler output, sumout and enables for
the various outputs. Page five registers are listed in the table below:
Table 7: IO Control Page Registers (Page 5)
ADDRESS NAME
16
Channel Input Mode
17
Resampler Input Mode
18
Resampler Output Mode
19
Sum IOMode
20
Serial Controller Modes
21
Serial Controller Frame
Count
22
Serial Controller Frame
Delays A and B
23
Serial Controller Frame
Delays C and D
24
Output Enables
25
26-31
Resampler Clock Divider
Unused
DESCRIPTION
Channel input format (packed, clock and frame polarity, parallel or serial).
Resampler input format (packed, clock and frame polarity, parallel or serial).
Controls resampler output clock rate, sync, polarity, and frame polarity.
Sum IO path rounding, delay, shifting, and clear.
Controls request clock rate, sync, and polarity.
Sets the serial controller’s frame length.
Delay positions for serial controller frame strobes A and B.
Delay positions for serial controller frame strobes C and D.
Output enables for sum, resampler, request, frame strobes, sync out, and
request polarities.
Sets the clock rate for the resampler computations
ADDRESS 16: Channel Input Mode Register, suggested default = 0x01
BIT
0 LSB
TYPE
R/W
NAME
PACKED
1
R/W
Unused
2
R/W
SCK_POL
3
R/W
SFS_POL
4
R/W
PARALLEL_A
5
R/W
PARALLEL_B
6
R/W
PARALLEL_C
7
R/W
PARALLEL_D
DESCRIPTION
Puts the channel serial inputs into the 32 bit transfer mode where each complex
pair is packed into 32 bit words. The complex pair is formatted as I word in the
upper 16 bits and the Q word in the lower 16 bits. Each word is formatted as
MSB first.
The SIN Input bits and SFS frame strobes are clocked in on the trailing edge of
SCK when this bit is set. The rising edge is used when this bit is low.
The SFS signal is treated as active low when this bit is set. Otherwise the signal
is treated as active high.
The parallel/Serial control for channel input A. When low input for channel A is
taken from the serial port. When high it is taken from the channel input page
registers.
The parallel/Serial control for channel B.
The parallel/Serial control for channel C.
The parallel/Serial control for channel D.
© 1999−2001 GRAYCHIP,INC.
- 34 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice