GC4116 Datasheet, PDF (50/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
6.6 AC CHARACTERISTICS
Table 16: AC Characteristics (-40 TO +85^oC Case, unless noted)
PARAMETER
SYMBOL
2.3 V to 2.7 V
MIN
MAX
UNITS
TEST
LEVEL
Clock Frequency
Clock low or high period
Clock Duty Cycle (t_CKH as a percentage of the clock period)
Clock rise and fall times (V_IL to V_IH)
Input setup before CK goes high (IN or SI)
Input hold time after CK goes high
Serial Clock Frequency
Serial Clock low or high period
Serial Data Setup before SCK
Serial Data Hold from SCK
Data output delay from rising edge of CK.
(OUT, CHREQ, RSREQ, QFLG or SO)
F_CK
Note 1 100
MHz
IV
t_CKL/H
3
ns
IV
70
%
II
t_RF
2
ns
I
t_SU
2
ns
IV
t_HD
0.8
ns
IV
F_SCK
0
100
MHz
IV
t_SCKL/H
3
ns
IV
t_SSU
2
ns
IV
t_SHD
0.8
IV
t_DLY
1
5
ns
IV
Output skew between SCCK and SCFS
t_SCSK
-2
2.5
ns
IV
Output skew between ROCK and ROFS or ROUT
t_ROSK
-2
2.5
ns
IV
JTAG Clock Frequency
F_JCK
0
40
MHz
IV
JTAG Clock low or high period
t_JCKL/H
10
ns
IV
JTAG Input (TDI or TMS) setup before TCK goes high
t_JSU
5
ns
IV
JTAG Input (TDI or TMS) hold time after TCK goes high
t_HD
10
ns
IV
JTAG output (TDO) delay from rising edge of TCK.
t_DLY
10
ns
IV
Control Setup before both CE, WR or RD go low (See section 3.1)
t_CSU
2
ns
IV
Control data setup during writes (edge mode). (See section 3.1)
t_EWCSU
4
ns
IV
Control hold after CE, WR or RD go high. (See section 3.1)
t_CHD
1
ns
IV
Control strobe (CE or WR) pulse width (Write operation). (See section 3.1)
t_CSPW
20
ns
IV
Control recovery time between reads or writes. (See section 3.1)
t_REC
20
ns
IV
Control output delay CE and RD low to C (Read Operation). (See section 3.1)
t_CDLY
12
ns
IV
Control tristate delay after CE and RD go high. (See section 3.1)
t_CZ
4
ns
I
Supply current
(F_CK =100MHz, N=9, all channels active). (See section 6.4)
I_CORE
395
mA
IV
Notes:
1. The minimum clock rate must satisfy F_CK/(4N) > 10KHz, where N is the CIC interpolation ratio.
2. Timing between signals is measured from mid-voltage (V_PAD/2) to mid-voltage. Output loading is a 50 Ohm transmission line.
Test Levels:
I. Controlled by design and process and not directly tested or recommended practice.
II. Verified on initial part evaluation.
III. 100% tested at room temperature, sample tested at hot and cold.
IV. 100% tested at hot, sample tested cold.
V. 100% tested at hot and cold.
© 1999−2001 GRAYCHIP,INC.
- 45 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice