GC4116 Datasheet, PDF (30/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
ADDRESS 3:
Interpolation Byte 0, suggested default = 0x07
BIT
TYPE
NAME
0-7
R/W
INT[0:7]
DESCRIPTION
The LSBs of the interpolation control word INT. INT is N-1.
ADDRESS 4:
Interpolation Byte 1, suggested default = 0x00
BIT
TYPE
NAME
0-5
R/W
INT[8:13]
6,7
R/W
Unused
DESCRIPTION
The 6 MSBs of the interpolation control word INT. INT is N-1.
Where INT is equal to N-1. The chip interpolates the input data by a factor of 2N for real input data and 4N for complex input
data, where N ranges from 8 to 16384. This provides an interpolation range from 32 to 65,536 for complex input signals and 16
to 32,768 for real input signals. NOTE: The chip needs to be flushed each time the interpolation registers are changed. See
Section 5.8. Values of N exceeding 1448 should be avoided since they will cause overflow unless the input signal amplitude is
correspondingly reduced. For complex output the signal is decimated by two after the CIC and before the mixer. As a result, the
effective interpolation amount is only N/2, but the gain needs to be calculated for “N”. The interpolation factor applies to all
channels in the chip.
In the SPLIT_IQ mode (see Section 3.3.4 and bit 1, address 1), INT is set to INT=2N-1, where N ranges from 4 to 8192.
ADDRESS 5:
Reset Register, Set to 0xff on power up.
BIT
0 LSB
1
2
3
4
5
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
NAME
RESET_A
RESET_B
RESET_C
RESET_D
RESAMPLER_RESET
NOCK_RESET
6
R/W
PAD_RESET
7
R/W
GLOBAL_RESET
DESCRIPTION
This bit resets channel A. It is set during power up. While in reset the channel
consumes very modest power (uWatts).
This bit resets channel B.
This bit resets channel C.
This bit resets channel D.
This bit resets the resampler.
Allows output enables to flow through registers in output pads. Set on power up
so that all outputs are tristated at power up. The user should reset this bit when
ready for outputs to drive.
This bit resets the output formatter block.
This bit powers down the chip.
The reset register powers up to the reset state of 0xff. The register should be set to 0xff during initialization, and then cleared
to begin operation. See Section 3.12 for initialization details.
© 1999−2001 GRAYCHIP,INC.
- 25 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice