GC4116 Datasheet, PDF (8/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
CE
WR
RD
A[0-4]
C[0-7]
CE
WR
RD
A[0-4]
C[0-7]
CE
WR
A[0-4]
C[0-7]
CE
WR
A[0-4]
C[0-7]
t_REC
t_CSU
t_CSU
t_CDLY
READ CYCLE- NORMAL MODE
t_REC
t_CZ
t_REC
t_CSU
t_CSU
t_CSPW
WRITE CYCLE- NORMAL MODE
t_REC
t_CHD
t_REC
t_CSU
t_REC
t_CSU
t_CDLY
READ CYCLE- RD HELD LOW
t_CSPW
WRITE CYCLE- RD HELD LOW
Figure 2. Normal Control I/O Timing
t_REC
t_CZ
t_REC
t_CHD
The edge write mode, enabled by the WRMODE input
pin, allows for rising edge write cycles. In this mode the data
on the C[0:7] pins only need to be stable for a small setup
time before the rising edge of the write strobe, and held for a
small hold time afterwards. This mode is appropriate for
processors that do not provide stable data before the start of
the write pulse. Figure 3 shows the timing for this mode.
The setup, hold and pulse width requirements for control
read or write operations are given in Section 6.0.
CE
WR
RD
A[0-4]
C[0-7]
t_REC
t_CSU
t_CSU
t_CSPW
EDGE WRITE MODE
t_CSU
Figure 3. Edge Write Control Timing
t_REC
t_CHD
© 1999−2001 GRAYCHIP,INC.
-3-
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice