GC4116 Datasheet, PDF (33/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
ADDRESS 14: Status Register
BIT
0 LSB
TYPE
R/W
NAME
CHAN_INPUT_READY
1
R/W
CHAN_MISSED
2
R/W
RES_INPUT_READY
3
R/W
RES_MISSED
4
R/W
CHAN_OVERFLOW
5
R/W
SUMIO_OVERFLOW
6
R/W
RES_OVERFLOW
7
R/W
CK_LOSS_DETECTED
DESCRIPTION
The user sets this bit after loading the input registers. The chip clears this
bit when the values have been read and it is time to load new ones. Part of
the channel’s parallel input handshake protocol.
The chip sets this bit If the user has not set the INPUT_READY bit before
the chip reads the input registers. This bit high indicates that an error has
occurred. Part of the channel’s parallel input handshake protocol.
The user sets this bit after loading the input registers. The chip clears this
bit when the values have been read and it is time to load new ones. Part of
the resampler’s parallel input handshake protocol.
The chip sets this bit If the user has not set the INPUT_READY bit before the
chip reads the input registers. This bit high indicates that an error has occurred.
Part of the resampler’s parallel input handshake protocol.
Overflow was detected in the CIC shifter.
Overflow was detected in the sumio path at the final rounder. For normal uses
this should not occur except in the final chip in a sumpath. In the final chip the
D/A loading is often optimized to balance clipping and rounding noise resulting
in a SUMIO_OVERFLOW every 10,000 to 100,000 samples.
This bit is set by the chip if an overflow is detected in the resampler. This should
never happen if the resampler is properly programmed.
The chip sets this bit if it detects a clock loss.
This register is modified by the chip setting or clearing bits to indicate status of a variety of conditions. The user reads the
status register to detect the status and rewrites it to be able to detect the next change in status.
The CHAN_INPUT_READY and RES_INPUT_READY bits are used to tell an external processor when to load new input
samples. If desired, the CHREQ and RREQ pins can be used as an interrupt to the external processor to tell the processor when
to load new samples. The user does not need to set the INPUT_READY bits if interrupts are used. If INPUT_READY is not set,
however, the MISSED flag will not be valid. The same input block design is used for channels and the resampler. The resampler
always requires complex input data. The channels can accept real input data. The parallel input mode assumes the data are
being entered as complex pairs, even when the data are real. To enter real data in the parallel mode, the user must put two real
samples into each complex pair, the first sample in the I-half and the second in the Q-half.
ADDRESS 15: Page Register
BIT
TYPE
NAME
0-5
R/W
Page[0:5]
6,7
R/W
Unused
DESCRIPTION
Page number for addresses 16 through 31.
© 1999−2001 GRAYCHIP,INC.
- 28 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice