GC4116 Datasheet, PDF (40/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
I/O CONTROL PAGE 5 (continue)
ADDRESS 17: Resampler Input Mode Register, suggested default = 0x03
BIT
0 LSB
TYPE
R/W
NAME
RES_PACKED
1
R/W
SC_MODE
2
R/W
RCK_POL
3
R/W
RFS_POL
4
R/W
RES_PARALLEL_A
5
R/W
RES_PARALLEL_B
6
R/W
RES_PARALLEL_C
7
R/W
RES_PARALLEL_D
DESCRIPTION
Puts the resampler serial inputs into the 32 bit transfer mode where each
complex pair is packed into 32 bit words. The complex pair is formatted as I word
in the upper 16 bits and the Q word in the lower 16 bits. Each word is formatted
as MSB first.
Set to zero when the serial controller is being used with the resampler and is set
to 1 when it is used with the channels.
The RIN Input bits and RFS frame strobes are clocked in on the trailing edge of
RSCK when this bit is set. The rising edge is used when this bit is low.
The RFS signal is treated as active low when this bit is set. Otherwise the signal
is treated as active high.
The parallel/Serial control for resampler input A. When low input for resampler
channel A is taken from the serial port. When high it is taken from the resampler
input page registers.
The parallel/Serial control for resampler channel B.
The parallel/Serial control for resampler channel C.
The parallel/Serial control for resampler channel D.
ADDRESS 18: Resampler Output Mode Register, suggested default = 0x51
BIT
0-3 LSB
TYPE
R/W
4
R/W
5
R/W
6,7
R/W
NAME
ROCK_RATE
ROCK_POL
ROFS_POL
ROCK_SYNC
DESCRIPTION
The resampler serial output clock rate is ROCK = CK/(1+ROCK_RATE). The
serial clock changes on the rising edge of CK when ROCK_RATE is even.
Resampler serial output clock polarity. Inverts ROCK. When ROCK_POL=0 and
ROCK_RATE=0, ROCK is a slightly delayed version of CK.
Resampler frame strobe polarity. If low, the frame strobe pulses high for one
RCK period prior to the first transmitted bit. If high the frame strobe pulses low.
Sync control for the resampler output clock. The sync settings are 0 =never; 1 =
SIA; 2 =SIB; 3=Always.
ADDRESS 19: Sum IOMode Register, suggested default = 0x80
BIT
0-2 LSB
TYPE
R/W
NAME
SUM_ROUND
3-5
R/W
SUM_SCALE
6
R/W
SUM_DELAY
7
R/W
SUM_CLEAR
DESCRIPTION
Round the output to 22-(2*SUM_ROUND) bits. The remaining low order bits are
cleared. In normal use SUM_ROUND is 0 for all chips in a sum path except the
final one. The final one is programmed to match the number of bits used by the
D/A or other follow-on devices.
Shift the sum output up by SUM_SCALE bits prior to rounding. In normal use
SUM_SCALE is 0 for all chips in a sum path except the final one. The final one is
typically programmed so that the output has a 14 dB crest factor.
The latency sumin to sumout is 8 cycles. Enabling this bit adds 8 cycles of
latency to the output of the 4 internal channels to match the delay from one
previous chip.
Clears sumin data so that regardless of the input to the sumin port it does not
affect the sum output.
© 1999−2001 GRAYCHIP,INC.
- 35 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice