GC4116 Datasheet, PDF (19/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
serial data streams. The RSTART pulse can only be one CK
pulse wide.
The resampler serial output format is shown in Figure
14. The serial frame sync (ROFS) and serial data (ROUT)
RSTART
ROCK
ROFS
ROUT
I15 I14 I13 I12 I11 I1 I0 Q15 Q14 Q13 Q12
Figure 14. Resampler Serial Output
change on the rising edge of the serial clock (ROCK). The
resampler serial outputs can be connected directly to the
upconverter channel serial inputs if the polarity of the
resampler serial clock is inverted by setting RES_CK_POL in
address 18 of the resampler control page.
3.7.8 Resampler I/O Control
The Resampler will stop if the output buffer is full, or if
the input buffer needs more samples. Typically the output
rate is constant, such as when the resampler is feeding
upconverter channels. The input rate is typically erratic,
depending upon when the resampler needs more input data.
The resampler start control (RSTART) is used to start
the serial outputs. The RSTART control transfers data from
the output buffer into the serial output registers. The serial
output frame will then start on the next rising edge of ROCK¹.
If the output buffer is full, then the resampler will stop until the
next RSTART pulse has been received.
The resampler input data timing is controlled by the
RREQ strobe and the Serial Controller described in the next
Section. The RREQ strobe is output when the resampler
needs more input data. The RREQ strobe should be
connected to the SCSTART input of the Serial Controller.
The Serial Controller is then programmed to tell the
resampler that the serial transfer is done and new input data
is ready. The frame length programmed into the Serial
Controller tells the resampler that the new data samples are
ready SC_FRAME_CNT+18 serial clocks after RREQ.
SC_FRAME_CNT is set in address 21 of the IO control page.
Note that the serial controller can be used to slow down the
RREQ rate by setting the minimum period between RREQ
strobes to be SC_FRAME_CNT+18 serial clocks.
1. Actually, the serial frame starts on the next rising edge of ROCK which is 2
CK pulses after RSTART.
3.8 SERIAL CONTROLLER
The Serial Controller block can be used to generate the
necessary serial clock and frame strobes for the channel or
resampler input ports. This frees the input data source
(ASIC, FPGA or DSP chip) from having to generate these
signals. In the case of a DSP chip, this may allow the input
samples to be transferred in a background “DMA” mode that
doesn’t interrupt the DSP before or after each serial transfer.
The Serial controller generates a serial clock and four
serial frame strobes, one for each input serial port. Each
frame strobe can be programmed to be delayed by a different
amount from the Serial Controller start (SCSTART) pulse.
The serial controller contains a serial clock generator
and a frame counter. The serial clock (SCCK) is generated
by dividing down CK by 1 to 16 (see SC_CK_DIV in address
20 of the IO control page). The serial clocks in multiple chips
can be synchronized by using the SIA or SIB sync inputs, as
selected by the SCCK_SYNC control bits in address 20 of
the IO control page. Two copies of the serial clock are output
on pins SCCK0 and SCCK1. Two copies are output to
increase the fanout of the clock.
The start signal (SCSTART) is clocked into the chip on
the rising edge of CK. SCSTART is expected to be one CK
clock cycle wide. Typically SCSTART is either connected to
CHREQ or RREQ, depending upon whether the it is being
used for the up convert channels or the resampler.
The 8 bit frame counter is started by SCSTART at the
value SC_FRAME_CNT. The counter is decremented at the
serial clock rate until it reaches zero. The counter will
continue to decrement for 18 more serial clocks if it is being
used with the resampler (SC_MODE=0 in address 17 of the
IO Control page), at which time it will tell the resampler that
the serial frame is done and a new resampler computation
can begin. The counter will count down 2 more serial clocks
and stop if the serial controller is being used with the
channels (SC_MODE=1).
The serial frame strobes SCFSA, SCFSB, SCFSC and
SCFSD are generated by comparing the upper four bits of
the frame counter to SC_FS_DELAY_A, SC_FS_DELAY_B,
SC_FS_DELAY_C and SC_FS_DELAY_D. A frame strobe
is output when the delay values match the counter and the
lower four bits of the counter are zero. This allows the frame
strobes to be generated on 16 serial clock boundaries.
NOTE: If the 4 LSBs of SC_FRAME_CNT are zero, and
one of the SC_FS_DELAY values match the upper 4 bits of
SC_FRAME_CNT, then that frame strobe will be active when
the serial controller is idle and waiting for another SCSTART
© 1999−2001 GRAYCHIP,INC.
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APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice