GC4116 Datasheet, PDF (18/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
using the FILTER_SEL controls in address 18 of the
resampler control page. The filter lengths are cut in half if the
filters are not symmetric. The coefficients are stored in
memory with h₀ stored in the lowest address, where h₀ is the
coefficient multiplied by the newest piece of data. The center
tap of a symmetric filter is h_(QTAP/2)-1. The coefficients for
multiple filters (NFILTER>1), are interleaved in the 256 word
memory.
3.7.4 Restrictions on NMULT
The user does not directly set the value of NDELAY. The
chip sets the value of NDELAY using NO_SYM_RES,
NMULT and NFILTER according to:
NDELAY = Floor_2[256-₍⁽--_N-²--_M--^–--_U-^N---_L-^O-_T--^_--₎-^S-₍--^Y-_N--^M-_F---_{I_}-_L--^R-_T--^E-_E---^SR---⁾-₎-]
where the function FLOOR_2[X] means the power of two
value that is equal to or less than “X”. Since NMULT is
restricted to be greater than or equal to 6 and less than or
equal to 64, then NDELAY is either 4, 8, 16, 32 or 64. The
length of the filter is then:
QTAP = (NDELAY)(NMULT)
The value of NMULT determines both the length of the
filter and the number of delays in the resampling operation.
In general one would choose the largest value of NMULT
which gives an adequately large value of NDELAY. The
choice of NMULT, however, must meet several restrictions.
NMULT must be greater than a minimum, it cannot exceed
the available number of multiplier cycles, and it must be less
than the input delay line segment size. These restrictions are
described below.
The minimum value of NMULT is determined by the
minimum number of clock cycles required to update the
resampler’s state. This is a hardware restriction imposed by
the chip’s architecture. This limitation is:
NMULT ≥ 6 if there are two or more channels
NMULT ≥ 7 if there is only one channel (NCHAN=0)
The maximum value of NMULT must be less than, or
equal to, twice the number of clock cycles available to
calculate a resampler output. NMULT is the number of
multiplier cycles used by the resampler to calculate each
output. Since the resampler can perform two multiplies every
clock cycle, the value of NMULT cannot exceed two times
the number of clock cycles available to the resampler for
each channel. The number of clock cycles available to the
resampler is equal to the clock rate to the chip divided by the
sum of the output sample rates for each resampler channel.
Note that the resampler’s output sample rate is usually much
less than the clock rate, so that NMULT is rarely limited by
this restriction.
The value of NMULT must also be less than the size of
the delay line formed by the input buffer. The size of the
delay line is either 16 for four resampler channels, 32 for two
channels or 64 for a single channel as set by the NCHAN
control in address 16 of the resampler control page. This
limits NMULT to be less than or equal to 15, 31 or 63
dependent upon the number of resampler channels¹.
The typical resampler configuration will have four active
channels, all using the same filter and the same resampling
ratio. The typical configuration has NCHAN set to 4,
NFILTER set to 1, NMULT set to 15 and NO_SYM_RES set
to 0. This sets NDELAY to 32 and QTAPS to 480.
3.7.5 Resampler Shift and Round
The gain of each resampler output is adjusted by an
up-shift by 0-15 bits (FINAL_SHIFT). This up-shift is applied
just before rounding to 12, 16, 20 or 24 bits (ROUND). The
values of FINAL_SHIFT and ROUND are set in control
register 19 of the resampler control page. The resampler
gain is:
RES_GAIN = ( -3---2---7---6-^R---8-^E---^S-_×---^_-_N--^S---_DU----_EM----_L---_A-----_Y---)(2^FINAL_SHIFT)
where RES_SUM is the sum of the QTAP coefficients.
3.7.6 By-Passing the Resampler
The resampler is bypassed by using a configuration
which has h₀ set to 1024, all other taps set to zero, NMULT
set to 7, NO_SYM_RES set to 1, FINAL_SHIFT set to 5, and
RATIO set to 2²⁶ (0x04000000). Note that the NDELAY term
in the RES_GAIN equation shown above does not apply in
this case and should be set to unity in the gain equation.
3.7.7 Resampler Output Buffer
The resampler output buffer stores resampler outputs
until they are needed. The output is double buffered so that
samples from each channel can be stored while previous
samples are being output. Resampler output samples are
held in the buffer until the RSTART signal is received. When
RSTART is received, the buffered data is transferred to the
serial output ports which begin to output the samples as
1. NOTE: If the resampler is being used at much less than its maximum
capacity, i.e., NMULT is much less than twice the number of clock cycles
available (See also RES_CLK_DIV), AND the channels are synchronous, then
NMULT may equal the size of the delay line.
© 1999−2001 GRAYCHIP,INC.
- 13 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice