GC4116 Datasheet, PDF (29/57 Pages) List of Unclassifed Manufacturers – MULTI-STANDARD QUAD DUC CHIP

GC4116 MULTI-STANDARD QUAD DUC CHIP
DATA SHEET REV 1.0
ADDRESS 0:
Sync Mode, suggested default = 0x69
BIT
0,1
(LSBs)
2,3
4,5
6
7
TYPE
R/W
R/W
R/W
R/W
R/W
NAME
INT_SYNC
COUNTER_SYNC
OUTPUT_SYNC
USE_ONESHOT
ONE_SHOT
DESCRIPTION
Synchronizes the interpolation control counter. The interpolation counter
controls the filtering of each channel. Mode 1 is SIA.
Synchronizes the sync counter. This counter is used to generate the periodic
“TC” sync pulses. Mode 2 is OS, not TC, for the counter. Mode 1 is SIA.
The selected sync is inverted and output on the SO pin. Mode 1 is SIA.
The terminal count mode in table 1 is replaced by ONE_SHOT (OS) when this
bit is set.
The one shot sync signal (OS) is generated when this bit is set. If OS_MODE in
register 13 is low, then a one shot pulse (one clock cycle wide) is generated. If
OS_MODE is high, then the ONE_SHOT sync is active while this bit is high. This
bit must be cleared before another one shot pulse can be generated.
ADDRESS 1:
Interpolation Mode, suggested default = 0x00
BIT
0 LSB
TYPE
R/W
NAME
REAL
1
R/W
SPLIT_IQ
2
R/W
GAIN_SYNC
3
R/W
TEST
4
R/W
NOSYM
5
R/W
DIAG
6,7
R/W
DIAG_SYNC
DESCRIPTION
The input samples are real when this bit is set and are up-converted as a single
sideband signal. The input samples are treated as complex when this bit is low.
The input rate is F_CK/4N when this bit is low and is F_CK/2N when this bit is high,
where F_CK is the chip’s clock rate and N is the interpolation setting in registers 3
and 4 (See Section 5.4). If double sideband real data is to be up-converted, then
the complex mode should be used with the Q-half set to zero.
This control bit puts all four channels into the SPLITIQ mode where each
channel processes real data at twice the input rate. Two channels work in
tandem (A with B and C with D) to process the complex input signal. This mode
allows the chip to upconvert two channels at double bandwidth. This mode is
used to provide UMTS transmit capability.
Selects when the input gain is updated. If 0 the input gain (see page 2) takes
effect immediately. If 1, then gain is updated on the first sample following SIB.
Special test mode. Set to 0 for normal use.
When 0 the PFIR filter is symmetric with 63 taps. When 1, the PFIR filter is
non-symmetric with 32 taps. The newest data sample is multiplied by h₃₁.
Use the diagnostic ramp as input data.
The diagnostic ramp is synchronized by the sync selected by these bits
according to table 1. This sync also loads the checksum register. Mode 1 is SIA
ADDRESS 2:
Interpolation Gain, suggested default = 0x09
BIT
TYPE
NAME
0-3
R/W
SCALE
4,5
R/W
BIG_SHIFT
6,7
R/W
UNUSED
DESCRIPTION
SCALE ranges from 0 to 15.
BIG_SHIFT equals 0, 1 or 2.
The CIC filter has a gain which is equal to N⁴. To remove this gain the CIC outputs are shifted down by
(3+SCALE+12*BIG_SHIFT) bits and then rounded to 16 bits before they are sent to the mixer circuit. The value chosen for
BIG_SHIFT must also satisfy: 2^{(12*BIG_SHIFT+18)} ≥ N^4. Overflows due to improper gain settings will go undetected if this
relationship is violated. This restriction means that BIG_SHIFT is 0 for N between 8 and 22, BIG_SHIFT is 1 for N between
23 and 181, and BIG_SHIFT is 2 for N between 182 and 1448. The interpolation gain settings apply to all channels in the
chip.
© 1999−2001 GRAYCHIP,INC.
- 24 -
APRIL 27, 2001
This document contains preliminary information which may be changed at any time without notice