STC5230 Datasheet, PDF (5/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
STC5230 Pin Description
All I/O is LVCMOS, except for CLK0 and CLK8, which are LVPECL.
Pin Name
Vdd33
Vdd18
Vss
AVdd18
AVss
TRST
TCK
TMS
TDI
TDO
RESET
MCLK
SPI_CS
SPI_SCK
SPI_SDI
SPI_SDO
EEP_SO
EEP_SI
EEP_SCK
EEP_CS
EVENT_INTR
REF1
REF2
REF3
REF4
REF5
REF6
Preliminary
Table 1: Pin Description
Pin #
I/O
Description
6,22,31,
44,59,61,
69,80,
87,97
9,18,27,
38,47,53,
60,65,84,
92
3.3V power input
1.8V power input
3,13,15,
20,29,35,
41,56,64,
67,71,78,
82,88,95
1, 76
75, 100
Digital ground
1.8V analog power input
Analog ground
94
I JTAG boundary scan reset, active low
93
I JTAG boundary scan clock
91
I JTAG boundary scan mode selection
90
I JTAG boundary scan data input
89
O JTAG boundary scan data output
30
I Active low to reset the chip
99
I Master clock input, 20 MHz
45
I SPI bus chip select (CS)
46
I SPI bus clock input (SCLK)
50
I SPI bus data input (SDI)
51
O SPI bus data output (SDO)
37
I/O Optional external EEPROM SO
36
I/O Optional external EEPROM SI
34
I/O Optional external EEPROM SCK
33
I/O Optional external EEPROM CS
32
O event interrupt
2
I Reference input 1
4
I Reference input 2
5
I Reference input 3
8
I Reference input 4
10
I Reference input 5
12
I Reference input 6
Data Sheet #: TM102 Page 5 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007