STC5230 Datasheet, PDF (15/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
SYNC bit
In external-timing mode (e.g., slave and synchro-
nized/master modes), this bit indicates the achieve-
ment of the synchronization. This bit won’t be
asserted in self-timing mode (e.g., freerun and hold-
over modes).
LOS bit
In external-timing mode (e.g., slave and synchro-
nized/master modes), this bit indicates the loss of sig-
nal of the active reference. This bit won’t be asserted
in self-timing mode (e.g., freerun and holdover
modes).
LOL bit
In external-timing mode (e.g., slave and synchro-
nized/master modes), the DPLL will raise the event of
loss of lock if it fails to achieve or maintain the lock to
the active reference. This bit won’t be asserted in
self-timing mode (e.g., freerun and holdover modes).
This bit is also not complemented to the SYNC bit.
Both bits won’t be asserted when the DPLL is still in
the pull-in process.
OOP bit
This bit indicates the out of pull-in range of the active
reference in external-timing mode (e.g., slave and
synchronized/master modes). This bit won’t be
asserted in self-timing mode (e.g., freerun and hold-
over modes). The frequency offset is centered on the
digitally calibrated freerun clock.
SAP bit
This bit indicates whether the DPLL’s output clocks
stop following the active reference because of the fre-
quency offset of the active reference is out of pull-in
range. The application can write to T(0/
4)_Control_Mode register to program whether the
DPLL shall follow the active reference out of the
specified pull-in range.
AHR bit
This bit indicates whether the device holdover history
is tracking on the current active reference (updating
by the long-term history).
Reference Input Monitoring and Qualifi-
cation
Functional Specification
The STC5230 accepts 12 external reference inputs at
8kHz, 64kHz, 1.544MHz, 2.048MHz, 19.44MHz,
38.88MHz, 77.76MHz, 6.48MHz, 8.192MHz,
16.384MHz, 25MHz, 50MHz, or 125MHz. Input fre-
quencies are detected automatically. The autode-
tected frequency of any reference may be read by
selecting the reference in the Ref_Selector register
(0x15) and then reading the frequency from register
Ref_Frq_Offset (0x17).
Each input is monitored and qualified for activity and
frequency offset. Activity monitoring is accomplished
with a leaky bucket accumulation algorithm, as shown
in figure 3. The “leaky bucket” accumulator has a fill
observation window that may be set from 1 to 16 ms,
where any hit of signal abnormality (or multiple hits)
during the window increments the bucket count by
one. The leak observation window is 1 to 16 times the
fill observation window. The leaky bucket accumulator
decrements by one for each leak observation window
that passes with no signal abnormality. Both windows
operate in a consecutive, non-overlapping manner.
The bucket accumulator has alarm assert and alarm
de-assert thresholds that can each be programmed
from 1 to 64.
Fill Observa-
tion Window,
1ms ~ 16ms
Frequency
Ref
Detector
Pulse
Monitor
Leaky
Bucket
Accumulator
Alarm Assert
Alarm De-Assert
Leak Observation
Window, 1~16 x Fill
Observation Window
Figure 3: Activity Monitor
Applications can write to the following registers to
configure the activity monitor: Fill_Obs_Window
(0x09), Leak_Obs_Window (0x0a), Bucket_Size
(0x0b), Assert_Threshold (0x0c), and
De_Assert_Threshold (0x0d).
HHA bit
This bit indicates the availability of the holdover his-
tory, which could be either the user provided history
or the device holdover history.
User can set the bucket size equal to 0 to turn off the
activity monitor. This de-asserts the activity alarms of
all the references. Otherwise, a non-zero bucket size
must be greater than or equal to the alarm assert
Preliminary
Data Sheet #: TM102 Page 15 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007