STC5230 Datasheet, PDF (27/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
Qualification_Timer, 0x14 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x14
Not used
Reference qualification timer, from 0 to 63 s.
Default value: 10
0 ~ 63 s
Ref_Selector, 0x15 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x15
Not used
1 ~ 12 (0x1 ~ 0xc)
Determines which reference data is displayed in register 0x16 and 0x17. Valid values from 1 to 12. Invalid val-
ues will not be written to the register.
Default value: 1
Ref_Frq_Offset, 0x16 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x16
Lower 8 bits of frequency offset
0x17
Reference frequency
Upper 4 bits of frequency offset
Displays the frequency offset and reference frequency for the reference selected by the Ref_Selector (0x15)
register. Frequency offset is from -204.7 to +204.7 ppm relative to calibrated freerun, in 0.1 ppm steps, two’s
complement. A value of -2048 indicates the reference is out of range.
The reference frequency is determined as follows (“Unknown” indicates a signal is present, but frequency is
undetermined):
0x17, bits 7 ~ 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Frequency
No signal
8 kHz
64 kHz
1.544 MHz
2.048 MHz
19.44 MHz
38.88 MHz
77.76 MHz
6.48MHz
8.192MHz
16.384MHz
25 MHz
50 MHz
125 MHz
Unknown
Reserved
Preliminary
Data Sheet #: TM102 Page 27 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007