STC5230 Datasheet, PDF (22/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
Processor Interface Descriptions
The STC5230 supports the serial SPI bus interface. The description of SPI bus’s interface timing is following:
The SPI interface bus mode uses the BUS_CS, BUS_ALE, BUS_RDB, and BUS_RDY pins, corresponding to
CS, SCLK, SDI, and SDO respectively, with timing as shown in figures 11 and 12:
Serial Bus Timing
CS
t_CS
t_CSHLD
t_CSMIN
t_CSTRI
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
t_Ds
t_Dh
t_CH
t_CL
SDI
SDO
A6 A5 A4 A3 A2 A1 A0 1
MSB
LSB
t_DRDY
t_DHLD
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Figure 11: Serial Bus Timing, Read access
CS
t_CS
t_CSHLD
t_CSMIN
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
t_Ds
t_Dh
t_CH
t_CL
SDI
A6 A5 A4 A3 A2 A1 A0
MSB
LSB
0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Figure 12: Serial Bus Timing, Write access
Preliminary
Data Sheet #: TM102 Page 22 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007