STC5230 Datasheet, PDF (21/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

checksum encryption is used in the configuration data
to assure the detection of transmission error.
Should the load fail, the application must reset the
device and repeat the load process.
Before the “bus ready” bit is asserted or after the
“load complete” bit in register Bus_Loader_Status is
asserted, all writes to the Bus_Loader_Data register
will be ignored.
At any time in the process, the application may read
the number of bytes that have been written from the
Bus_Loader_Counter register.
EEPROM Load Process
When LM is configured as EEP_LOAD_MODE, the
configuration data will be loaded from the optional
external EEPROM by device’s build-in EEPROM
loader automatically. Application shall read and check
the register EEP_CHECKSUM which indicates the
CRC-16 checksum status of the loading process. If
the download failed, the application must reset the
device and repeat the check of this status again.
EEPROM: Read and Write
Application has to pump the configuration data into
the external EEPROM before the normal operation if
expecting to configure to load the data from
EEPROM.
When LM is configured as EEP_LOAD_MODE, the
application may read and write the configuration data
from/to the external EEPROM via device’s EEPROM
controller using the register EEP_Controller_Mode,
EEP_Controller_Cmd, EEP_Controller_Page, and
EEP_Controller_Data (0x71 to 0x74).
After pump (writing) the whole configuration data into
the external EEPROM, application has to read it back
and do the comparison to ensure no transmission
error happened. The writing and reading procedures
are as follows:
Procedure EEP_Write
begin
/* --- *
The data array data[10496] contains the hardware/
firmware configuration data, starting from index 0.
* --- */
STC5230
Synchronous Clock for SETS
Data Sheet
- busy wait until bit “ready” in register
EEP_Controlle_Fr__uM_no_cde_tii_os e_nq_aua_ll _Sto_p‘1_e’; _cification
- write 0x01 to register EEP_Controller_Mode;
/* turn on the write feature */
- write 0x00 to register EEP_Controller_Cmd;
/* reset the page FIFO buffer */
- for i = 0 to 163 step 1
begin
- write (i) to register EEP_Controller_Page;
/* set the page index */
- for j = 0 to 63 step 1
begin
- write data[64*i+j] to register
EEP_Controller_Data;
end
- write 0x01 to register EEP_Controller_Cmd;
/* issue the write command */
- busy wait until bit “ready” in register
EEP_Controller_Mode is equal to ‘1’;
end
- write 0x00 to register EEP_Controller_Mode;
/* turn off the write feature */
end of procedure EEP_Write
Procedure EEP_Read
begin
- busy wait until bit “ready” in register
EEP_Controller_Mode is equal to ‘1’;
- for i = 0 to 163 step 1
begin
- write (i) to register EEP_Controller_Page;
/* set the page index */
- write 0x02 to register EEP_Controller_Cmd;
/* issue the read command */
- busy wait until bit “ready” in register
EEP_Controller_Mode is equal to ‘1’;
- for j = 0 to 63 step 1
begin
- read and copy the value of register
EEP_Controller_Data into data[64*i+j];
end
end
/* --- *
The data array data[10496] is then carrying the hard-
ware/firmware configuration data, starting from index
0.
* --- */
end of procedure EEP_Read
Preliminary
Data Sheet #: TM102 Page 21 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007