STC5230 Datasheet, PDF (28/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Refs_Activity, 0x18 (R)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
0x18
Ref 8
Ref 7
Ref 6
Ref 5
0x19
Not used
T4_XSYNC_INT0_XSYNC_IN
Reference activity indicator, 0 = no activity, 1 = activity.
Bit3
Ref 4
Ref 12
Bit2
Ref 3
Ref 11
Bit1
Ref 2
Ref 10
Bit0
Ref 1
Ref 9
Refs_Qual, 0x1a (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
0x1a
Ref 8
Ref 7
Ref 6
Ref 5
Ref 4
0x1b
Not used
Ref 12
Reference qualification indicator, 0 = not qualified, 1 = qualified.
Bit2
Ref 3
Ref 11
Bit1
Ref 2
Ref 10
Bit0
Ref 1
Ref 9
T0_Control_Mode, 0x1c (R/W)
Address
0x1c
Bit7
Bit6
Not used
Mode control bits for T0.
Bit5
OOP: Out
of Pull-in
range:
0=Follow
1=Don’t fol-
low
Bit4
Manual/
Auto
0=Manual
1=Auto
Bit3
Revertive
0=Non-
revertive
1=Rever-
tive
Bit2
HO_Usage
0=DHH
1=User
Bit1
Not used
Bit0
Phase
Align Mode
0=Arbitrary
1=Align
Phase Align Mode
HO_Usage
OOP
0 = Arbitrary (use initial phase), 1 = Phase align
0 = Device Holdover History (DHH) is used; 1 = User supplied history is used.
In manual mode, when the selected active reference is out of the pull-in range, as
specified in register Disqualification_Range (0x10). OOP will determine if the ref-
erence is to be followed, 0 = Follow, 1 = Don’t follow.
Default value: 0
T0_Bandwidth, 0x1d (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x1d
Not used
Sets the T0 loop bandwidth:
Bandwidth select
0x1d, bits 4 ~ 0
0
1
2
3
4
5
Bandwidth, Hz
107
50
24
12
5.9
2.9
Preliminary
Data Sheet #: TM102 Page 28 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007