STC5230 Datasheet, PDF (29/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Default value: 6
0x1d, bits 4 ~ 0
6
7
8
9
10
31 ~ 11
STC5230
Synchronous Clock for SETS
Data Sheet
Bandwidth, Hz
1.5
.73
0.37
0.18
0.09
Reserved
T0_Auto_Active_Ref, 0x1e (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x1e
Not used
Selection
Indicates the automatically selected active reference for T0, when this T0 is a “master”. When this T0 is a
“slave”, the master’s active reference is indicated. (Data valid in automatic mode only)
Bit 3 ~ Bit 0
0
1 ~ 12
13
14, 15
T0_Manual_Active_Ref, 0x1f (R/W)
Selection
Freerun
Sync with Ref 1 ~ Ref 12
Holdover
Reserved
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x1f
Not used
Selects the active reference for T0 in manual reference select mode.
Selection
Default value: 0
Bit 3 ~ Bit 0
0
1 ~ 12
13
14, 15
Selection
Freerun
Sync with Ref 1 ~ Ref 12
Holdover
Reserved
T0_Device_Holdover_History, 0x20 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x20
Bits 0 - 7 of 32 bit Device Holdover History
0x21
Bits 8 - 15 of 32 bit Device Holdover History
0x22
Bits 16 - 23 of 32 bit Device Holdover History
0x23
Bits 24 - 31 of 32 bit Device Holdover History
Device holdover history for T0 relative to MCLK. 2’s complement. Resolution is 0.745x10^-3ppb.
Default value: 0
Preliminary
Data Sheet #: TM102 Page 29 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007