STC5230 Datasheet, PDF (34/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
Device holdover history for T4 relative to MCLK. 2’s complement. Resolution is 0.745x10^-3ppb.
Default value: 0
T4_Long_Term_Accu_History, 0x41 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x41
Bits 0 - 7 of 32 bit Long Term History
0x42
Bits 8 - 15 of 32 bit Long Term History
0x43
Bits 16 - 23 of 32 bit Long Term History
0x44
Bits 24 - 31 of 32 bit Long Term History
Long term accumulated history for T4 relative to MCLK. 2’s complement. Resolution is 0.745x10^-3 ppb.
T4_Short_Term_Accu_History, 0x45 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x45
Bits 0 - 7 of 32 bit Short Term History
0x46
Bits 8 - 15 of 32 bit Short Term History
0x47
Bits 16 - 23 of 32 bit Short Term History
0x48
Bits 24 - 31 of 32 bit Short Term History
Short term accumulated history for T4 relative to MCLK. 2’s complement. Resolution is 0.745x10^-3 ppb.
T4_User_Accu_History, 0x49 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x49
Bits 0 - 7 of 32 bit User Holdover History
0x4a
Bits 8 - 15 of 32 bit User Holdover History
0x4b
Bits 16 - 23 of 32 bit User Holdover History
0x4c
Bits 24 - 31 of 32 bit User Holdover History
User accumulated history for T4 relative to MCLK. 2’s complement. Resolution is 0.745x10^-3 ppb.
Default value: 0.
T4_History_Ramp, 0x4d (R/W)
Address
0x4d
Bit7
Bit6
Bit5
Bit4
Not used Long Term History bandwidth
Holdover bandwidth and ramp controls for T4:
Bit3
Bit2
Short Term History band-
width
Bit1
Bit0
Ramp control
Preliminary
0x4d, bits 6 ~ 4
000
001
010
Long Term
History -3dB
Bandwidth
9.7 mHz
4.9 mHz
2.4 mHz
Data Sheet #: TM102 Page 34 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007