STC5230 Datasheet, PDF (17/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
and pre-empt the existing active reference. This is
determined by either enabling or disabling the “rever-
tive” bit of the T(0/4)_Control_Mode (0x1c/0x39) to
“1” for revertive or to “0” for non-revertive operation.
When reversion (pre-emption) is enabled, the candi-
date reference will be selected immediately as the
new active reference. When reversion is disabled, the
current active reference will not be pre-empted by any
candidate until it is disqualified.
The automatically selected active reference for each
DPLL may be read from T(0/4)_Auto_Active_Ref
(0x1e/0x3b) registers.
The pre-qualification scheme is described in the Ref-
erence Inputs Monitoring and Qualification sec-
tion.
Output Clocks
The clock output section includes 4 timing genera-
tors, an APLL, and four dividers, and generates eight
synchronized clocks, as shown in figure 5.
T0 DPLL
Clk
Synthesizer
APLL
Clk0
155.52/125MHz
Clk1 _{19.44/38.88/77.76/}
Divider
51.84/25/50/125 MHz
Divider ^{Clk2 19.44/38.88/77.76/}
51.84/25/50/125 MHz
Clk3
Divider
8 kHz
Clk4
Divider
2 kHz
Clk8 _{155.52/125MHz}
Clk
Clk5
Synthesizer
DS3, E3
Clk
Clk6 _{nxDS1, nxE1}
Synthesizer
n = 1,2,4,8,16
T4 DPLL
Clk
Clk7
T1, E1
Synthesizer
Figure 5: Output Clocks
The first synthesizer drives an analog PLL and gener-
ates six output clocks. It is driven from the T0 DPLL:
• CLK0: 155.52/125 MHz (LVPECL), selected
or disabled by writing the CLK0_Sel register
(0x56).
• CLK1: Programmable at 19.44MHz,
38.88MHz, 51.84MHz, 77.76 MHz, 25MHz,
50MHz, 125MHz, and disabled, by writing to
the CLK1_Sel register (0x57).
• CLK2: Programmable at 19.44MHz,
38.88MHz, 5F1u.8n4c, 7ti7o.7n6aMl HSzp,e2c5iMfiHcza,tion
50MHz, 125MHz, and disabled, by writing to
the CLK2_Sel register (0x58).
• CLK3: 8kHz, 50% duty cycle or programma-
ble pulse width, and may be disabled by writ-
ing to the CLK3_Sel register (0x59).
• CLK4: 2kHz, 50% duty cycle or programma-
ble pulse width, and may be disabled by writ-
ing to the CLK4_Sel register (0x5a).
• CLK8: the second pair of 155.52/125 MHz
(LVPECL), selected or disabled by writing the
CLK8_Sel register (0x65).
Two more synthesizers generate additional clocks
from the T0 DPLL:
• CLK5: Either DS3 or E3 rate, or “disabled”,
programmed by writing to the CLK5_Sel reg-
ister (0x5b).
• CLK6: Programmable at nxDS1 or nxE1 rate,
where n=1,2,4,8,16, or may be disabled, by
writing to the CLK6_Sel register (0x5c).
One synthesizer is driven by the T4 DPLL:
• CLK7: Either DS1 or E1 rate, or “disabled”,
programmed by writing to the CLK7_Sel reg-
ister (0x5d), bits 0 - 1.
When a clock output is disabled, the pin is tri-stated.
In addition, the T0_XSYNC_OUT output provides
phase information and state data for master/slave
operation of the T0 timing generators. The
T4_XSYNC_OUT output provides an 8kHz signal for
master/slave operation of the T4 timing generator.
Note that CLK0,1, 2, 5, 6 and 8 are phase aligned
with CLK3 (8kHz) as shown in Figure 6. CLk3 is
phase aligned with CLK4 (2kHz).
2kHz
8kHz
38.88MHz
77.76MHz
T1/E1
T3/E3
Figure 6: T0 clock output Phase Alignment
Preliminary
Data Sheet #: TM102 Page 17 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007