STC5230 Datasheet, PDF (35/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

0x4d, bits 6 ~ 4
011
100
101
STC5230
Synchronous Clock for SETS
Data Sheet
Long Term
History -3dB
Bandwidth
1.2 mHz
0.61 mHz
0.30 mHz
0x4d, bits 3 ~ 2
00
01
10
11
Short Term
History -3dB
Bandwidth
2.5 Hz
1.24 Hz
0.62 Hz
0.31 Hz
0x4d, bits 1 ~ 0
00
01
10
11
Default value: 0x27 (2.4mHz; 1.24Hz; 2ppm/s)
Ramp control
No Control
1 ppm/s
1.5 ppm/s
2 ppm/s
T4_Priority_Table, 0x4e (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x4e
Ref 2 Priority
Ref 1 Priority
0x4f
Ref 4 Priority
Ref 3 Priority
0x50
Ref 6 Priority
Ref 5 Priority
0x51
Ref 8 Priority
Ref 7 Priority
0x52
Ref 10 Priority
Ref 9 Priority
0x53
Ref 12 Priority
Ref 11 Priority
Reference priority for automatic reference selection mode. Lower values have higher priority:
Default value: 0
0x4e - 0x53, 4 bits
0000
0001 ~ 1111
Reference Priority
Disable reference
1 ~ 15
T4_PLL_Status, 0x54 (R)
Address
0x54
Bit7
HHA
1=Available
0=Not
available
Bit6
AHR
1=Ready
0=Not
ready
Bit5
Reserved
Bit4
SAP
1=Stop at
pull-in
range
0=Follow-
ing
Bit3
OOP
1=Out of
pull-in
range
0=In range
Bit2
LOL
0=No LOL
1=LOL
Bit1
LOS
0=No LOS
1=LOS
Bit0
SYNC:
0=No Sync
1=Sync
Preliminary
Data Sheet #: TM102 Page 35 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007