STC5230 Datasheet, PDF(14/48 Page) Connor-Winfield Corporation

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STC5230 Datasheet, PDF (14/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

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STC5230

Synchronous Clock for SETS

Data Sheet

Freerun

No Reference

Available and

HO not Available

Any

Reference

Available

Locking

Frequency

Locked

Synchronized

No Reference Available

and HO Available

Switch to a

new active

reference

Any

Reference

Available

Holdover

Figure 2: Operating mode transition in auto-

matic reference selection (Master mode)

History Accumulation Details

Three holdover histories are built and maintained by

each timing generator: the short-term history, the

long-term history, and the device holdover history.

1. Short-Term History

This is a short-term average frequency of DPLLâs

clock outputs of all time. The weighted single-pole

low-pass filter may be programmed for a -3dB point of

2.5, 1.24, 0.62, or 0.31 Hz by writing to the T(0/

4)_History_Ramp register (0x30/0x4d). The short-

term history is used in the zombie sub-mode. This

history may be read from the T(0/

4)_Short_Term_Accu_History registers (0x28-0x2b/

0x45-0x48).

2. Long-Term History

This is a long-term average frequency of DPLLâs

clock outputs, while synchronized to a selected exter-

nal reference. The weighted single-pole low-pass fil-

ter may be programmFuedncfotrioan-a3dl BSppoeinctifoifc9a.t7i,o4n.9,

2.4, 1.2, 0.61, or 0.31 mHz by writing to the T(0/

4)_History_Ramp register (0x30/0x4d). Internally, an

express mode is used after reset by applying a lower

time constant for the first 15 minutes to speed up the

history accumulation process. This accumulation pro-

cess will be reset whenever the selected reference is

switched or loss of lock occurs. The accumulation

process will then resume after the synchronization

achieved - the assertion of âSYNCâ bit in the T(0/

4)_DPLL_Status register (0x37/0x54). Additionally,

the application may flush/rebuild this long-term his-

tory by writing either â0â or â1â to the T(0/

4)_Accu_Flush register (0x38/0x55). The long-term

history may be read from the T(0/

4)_Long_Term_Accu_History registers (0x24-0x27/

0x41-0x44).

3. Device Holdover History

When the timing generator enters the holdover mode

with the history usage programmed as Device Accu-

mulated History Holdover Mode, this history deter-

mines the CLK(0-6,8) (CLK7 for T4) clock outputs.

The initial history will begin and continuously being

updated by the long-term history after the 15 minute

express mode time has completed. Updating will stop

if the long term history accumulation process is reset

as a result of a reference switch or loss of lock. Thus,

the previous holdover history will persist until a new

long term history is accumulated following a refer-

ence switch or the attendant re-building of the long

term history after loss of lock. The âAHRâ bit of the

T(0/4)_DPLL_Status registers (0x37/0x54) is set to

â1â during updating, but will revert to â0â when updat-

ing stops. Additionally, the application may reset this

holdover history by writing â1â to the T(0/

4)_Accu_Flush register (0x38/0x55).

Phase-Locked Loop Status Details

The T(0/4)_PLL_Status registers (0x37/0x54) con-

tain the detailed status of DPLL, including the signal

activity of the active reference, the synchronization

status, and the availability of the holdover histories.

Applications can program the Intr_Enable register to

enable/disable the interrupts (pin EVENT_INTR)

trigged by the status change of T(0/4)_PLL_Status

registers.

Preliminary

Data Sheet #: TM102 Page 14 of 48

Rev: P01

Date: August 22, 2007

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