STC5230 Datasheet, PDF (39/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Selects or disables the CLK7 output.
STC5230
Synchronous Clock for SETS
Data Sheet
Default value: 2
0x5d, bits 1 ~ 0
0
1
2
3
CLK7 output
Disabled
1.544MHz (T1)
2.048MHz (E1)
Reserved
Intr_Event, 0x5e (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5e
Event 7:
T4 cross
reference
changed
from non-
active to
active
Event 6:
T4 cross
reference
changed
from active
to non-
active
Event 5:
T4 DPLL
status
changed
Event 4:
T4 active
reference
changed in
auto selec-
tion mode
Event 3:
T0 cross
reference
changed
from non-
active to
active
Event 2:
T0 cross
reference
changed
from active
to non-
active
Event 1:
T0 DPLL
status
changed
Event 0:
T0 active
reference
changed in
auto selec-
tion mode
0x5f
Event 9:
Event 8:
Any refer- Any refer-
ence
ence
changed
changed
from dis-
qualified to
qualified
from quali-
fied to dis-
qualified
Interrupt event, 0 = no event, 1 = event occurred. Interrupt 8 and 9 apply to the 12 reference inputs only.
Interrupts are cleared by writing “1’s” to the bit positions to be cleared (See General Register Operation,
Clearing bits in the Interrupt Status Register section).
Intr_Enable, 0x60 (R/W)
Address
0x60
0x61
Bit7
Intr 7
Enable
Bit6
Intr 6
Enable
Bit5
Intr 5
Enable
Bit4
Intr 4
Enable
Interrupt disable/enable, 0 = disable, 1 = enable.
Default value: 0
Bit3
Intr 3
Enable
Bit2
Intr 2
Enable
Bit1
Intr 1
Enable
Intr 9
Enable
Bit0
Intr 0
Enable
Intr 8
Enable
T0_MS_PHE, 0x62 (R)
Address
Bit7
0x62
0x63
0x64
Bit6
Bit5
Not used
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 0 - 7 of 20 bit Phase Delay
Bits 8 - 15 of 20 bit Phase Delay
Bits 16 - 19 of 20 bit Phase Delay
Preliminary
Data Sheet #: TM102 Page 39 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007