STC5230 Datasheet, PDF (18/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
Master/Slave Configuration
Pairs of STC5230 devices may be operated in a mas-
ter/slave configuration for added reliability, as shown
in Figure 7.
Devices are configured as master/slave pair by cross-
connecting their respective T(0/4)_XSYNC_OUT and/
or T(0/4)_XSYNC_IN pins. The T(0/4)_MS pins deter-
mine the master or slave mode for each timing gener-
ator: 1=Master, 0=Slave. Thus, master/slave state is
always manually controlled by the application. The
slave T0 synchronizes and phase-aligns in the 2kHz
domain according to data received over the
T0_XSYNC_OUT / T0_XSYNC_IN data link from the
paired partner. The slave T4 synchronizes and
phase-aligns to the 8kHz received on the
T4_XSYNC_OUT / T4_XSYNC_IN connection from
the paired partner as well.
T0_MS
T4_MS
T0 PLL ^T0_XSYNC_OUT
T0 PLL
T0_XSYNC_IN
T4 PLL
T4_XSYNC_OUT
T4_XSYNC_IN
T4 PLL
STC5230
STC5230
T0_MS
T4_MS
Figure 7: Master/Slave Pair
The T0 and T4 may be operated completely indepen-
dent of each other – either or both may be cross-con-
nected as master/slave pairs across two STC5230
devices, and master/slave states may be set the
same or opposite within a given device.
When two STC5230 are wired in the master/slave
pair configuration, the paired T0 timing generators
can be running in master/master, master/slave, or
slave/master modes. However, running in slave/slave
mode will not be disable due to the clock resonance
of the closed loop. Same applies to the paired T4 tim-
ing generators.
The T0_T4_MS_Sts register reflect the states of the
T(0/4)_MS pins.
Master/Slave Operation
While in the slave configuration, the operation is anal-
ogous to the synchronized/master mode. The T(0/
4)_XSYNC_OUT daFtaulninckt/8iokHnzalsSigpnaelscipfircovaitdieonthe
phase information of 2kHz (T0) and 8kHz (T4) for
phase alignment between the master and the slave.
In addition to phase information, T0_XSYNC_OUT
also provides the reference selection state to ensure
that later the new master may lock on the same refer-
ence if reference selection is in “automatic” mode.
Perfect phase alignment of the Clk(x) output clocks
(between the paired timing generators in two devices)
would require no delay on the cross-couple data link
connection. To accommodate delay on the path, the
STC5230 provides a programmable phase compen-
sation feature. See figures 8 and 9. The slave’s
Clk(x) outputs may be phase shifted from 0 to
+409.5ns, in 100ps increments according to the con-
tents of the T(0/4)_Slave_Phase_Adj (0x05/06,
0x07/08) registers to compensate for the path delay
of the T(0/4)_XSYNC_OUT to T(0/4)_XSYNC_IN
connections. This offset may therefore be pro-
grammed to exactly compensate for the actual path
delay associated with the particular application's
cross-couple traces. Thus, master/slave switches
with the STC5230 devices may be accomplished with
near-zero phase hits to the downstream devices.
Master T0
Clock
Synthesizer
STC5230
2kHz
8kHz
38.88MHz
77.76MHz
T1/E1
T3/E3
Slave T0
Clock
Synthesizer
STC5230
2kHz
8kHz
38.88MHz
77.76MHz
T1/E1
T3/E3
Programmable compensation
from 0 to 409.5 ns
Figure 8: T0 CLK0-6,8 Phase Alignment and
Master/Slave skew Control
STC5230 is capable to trace and report the round-trip
phase delay of T0’s cross-couple links. While T0 is
configured as in master mode in redundant applica-
tion, the phase delay between T0_XSYNC_OUT and
Preliminary
Data Sheet #: TM102 Page 18 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007