STC5230 Datasheet, PDF (40/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
T0’s phase delay of the round-trip cross-couple links from the master to the slave then back to the master. 2’s
complement. Resolution is (12.5ns/64 ~= 0.2ns). Range from (-125us/2) to (+125us/2). This value is valid only
when T0 is configured as in master mode.
CLK8_Sel, 0x65 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x65
Selects or disables the CLK8 output.
Default value: 0
Not used
CLK8 Select
0x65, bits 1 ~ 0
0
1
2
3
CLK8 output
Disabled
155.52MHz
125MHz
Reserved
Bus_Loader_Status, 0x70 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x70
Not used
load
bus ready Checksum
complete
status
If bus load data mode has been selected with pins LM0,1, this register Indicates the loader’s status.
load complete
bus ready
checksum status
Set to 1 when the loading process is complete in the bus load mode.
Set to 1 when the device is ready to load data in the bus load mode.
Set to 1 if the data load is successful (CRC-16 checksum over the 10,496 bytes of
configuration data passes) in the bus load data mode. The “checksum status” bit is
valid only after the “load complete” bit has been set.
Bus_Loader_Data, 0x71 (W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x71
Data
If bus load data mode has been selected with pins LM0,1, the hardware and firmware configuration data is writ-
ten to this register.
Bus_Loader_Counter, 0x72 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x72
Bits 0 -7
0x73
Not used
Bits 8 - 13
If bus load data mode has been selected with pins LM0,1, this register indicates the number of bytes that have
been written to the Bus_Loader_Data register.
Preliminary
Data Sheet #: TM102 Page 40 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007