STC5230 Datasheet, PDF (36/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

SYNC
LOS
LOL
OOP
AHR
HHA
SAP
HHA
1
1
0
0
STC5230
Synchronous Clock for SETS
Data Sheet
Indicates synchronization has been achieved
Loss of signal of the active reference
Loss of lock (Failure to achieve or maintain lock)
Out of pull-in range
Active Holdover History Ready
Holdover History Available
Indicates the output clocks stop following the selected reference, caused by out of pull-in
range
AHR
1
0
0
1
Holdover Status
Holdover History available: Device Holdover History tracking on the current active reference
Holdover History available: Device Holdover History based on last available history
Holdover History not available
Not applicable
T4_Accu_Flush, 0x55 (W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x55
Not used
HO flush
Writing to this register will perform a flush of the accumulated history. The value of bit zero determines which
histories are flushed. Bit 0 = 0, Flush and reset T4 long term history only; bit 0 = 1, flush/reset both T4 long
term history and the T4 device holdover history.
CLK0_Sel, 0x56 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x56
Selects or disables the CLK0 output.
Default value: 0
Not used
CLK0 Select
0x56, bits 1 ~ 0
0
1
2
3
CLK0 output
Disabled
155.52MHz
125MHz
Reserved
CLK1_Sel, 0x57 (R/W)
Address
Bit7
Bit6
0x57
Selects or disables the CLK1 output.
Bit5
Bit4
Bit3
Not used
0x57, bits 2 ~ 0
0
1
CLK1 output
Disabled
19.44MHz
Bit2
Bit1
Bit0
CLK1 Select
Preliminary
Data Sheet #: TM102 Page 36 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007