STC5230 Datasheet, PDF (12/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
Detailed Description
Chip Master Clock Input
The device operates with an external 20MHz OCXO
or TCXO as its master clock, connected to the MCLK
input, pin 99.
The freerun clock may be digitally calibrated from
MCLK by writing an offset to the Freerun_Cal regis-
ter, (0x0e/0f), from -102.4 to +102.3 ppm, in 0.1ppm
steps, in two’s complement form. (See Register
Descriptions section for details regarding register
references in this section.)
Operating Mode General Description
The STC5230 includes both a T0 and T4 timing gen-
erators. Each timing generator has its own DPLL.
In general, each timing generator could either be in
external-timing or self-timing mode individually. In
external-timing, a timing generator may select any of
the external references as the active reference for the
DPLL. The active reference can be either one of the
12 input reference clocks, or the reference from the
T(0/4)_XSYNC_IN cross-couple links in slave mode.
In addition, T4 may select the clock output of T0 as its
active reference. In self-timing, the clock outputs are
synthesized from the MCLK (the external TCXO/
OCXO) with a certain calibration or a given frequency
offset.
In master mode, the timing generators may each
operates in the Freerun, Synchronized, or Holdover
mode. Slave mode is analogous to the synchronized/
master. Both are in external-timing. In synchronized/
master mode, the phase relation between the refer-
ence and the clock outputs could be configured as
arbitrary or aligned. User could also program DPLL’s
loop bandwidth to vary the noise transfer function. In
slave mode, the clock outputs phase-align to the
cross-reference. Unlike in master mode, the loop
bandwidth is fixed (107 Hz) in slave mode.
Holdover mode is analogous to the freerun mode.
Both are in self-timing. The clock outputs are synthe-
sized from the local oscillator with a certain calibration
or a given frequency offset. The stability in these two
modes is simply determined by the local oscillator.
Operating Mode Details
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puts to the downstream devices, even under the
change of operating mode or reference switch. Both
the phase and frequency transition will be continuous.
The transfer into the self-timing mode (freerun and
holdover) is designed to be free of frequency bump. A
frequency ramp control limits the rate of frequency
change when transferring in and out of self-timing
mode.
Freerun/Master Mode
The CLK(0-6,8) (CLK7 for T4) clock outputs are syn-
thesized and may be calibrated from MCLK and have
the stability of the external TCXO/OCXO. The calibra-
tion offset may be programmed by the application by
writing to the Freerun_Cal register, (0x0e/0f). The
calibration offset may be programmed from -102.4 to
+102.3 ppm, in 0.1ppm steps.
On all transitions into freerun or back from freerun, an
application programmable maximum slew rate of 1,
1.5, or 2 ppm/second (or no slew rate limit) is applied,
as written to the T(0/4)_History_Ramp registers
(0x30/ 0x4d).
Holdover/Master Mode
Holdover Mode is analogous to the freerun mode.
The CLK(0-6,8) (CLK7 for T4) clock outputs are syn-
thesized from MCLK with a given frequency offset,
which is centered on the digitally calibrated freerun
clock. The clock outputs will have the stability of the
external TCXO/OCXO. The application may select
the source of the frequency offset from either a device
accumulated holdover history or a user supplied fre-
quency offset by writing the “HO_Usage” bit of the
T(0/4)_Control_Mode register (0x1c/0x39). If the bit
is set to Device Accumulated History Holdover
Mode, the DPLL will use the device accumulated
device holdover history to synthesize the clock out-
puts. If the bit is set to User Supplied History Mode,
the DPLL outputs are synthesized according to an
application supplied frequency offset, as provided in
the T(0/4)_User_Accu_History registers (0x2c/
0x49). To facilitate the user’s accumulation of a hold-
over history, the user may read the short-term history
of the current clock outputs from the T(0/
4)_Short_Term_Accu_History register (0x28-0x2b/
0x45-0x48).
Preliminary
Data Sheet #: TM102 Page 12 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007